Simulation Results: csrng

 
05/08/2026 15:30:30 DVSim: v1.50.0 sha: 023bd59 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 85.47 %
  • code
  • 92.13 %
  • assert
  • 93.23 %
  • func
  • 71.04 %
  • block
  • 96.85 %
  • line
  • 97.52 %
  • branch
  • 92.18 %
  • toggle
  • 93.10 %
  • FSM
  • 85.71 %
Validation stages
V1
100.00%
V2
91.67%
V2S
87.50%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
csrng_smoke 3.000s 47.319us 1 1 100.00
csr_hw_reset 1 1 100.00
csrng_csr_hw_reset 2.000s 38.867us 1 1 100.00
csr_rw 1 1 100.00
csrng_csr_rw 2.000s 20.374us 1 1 100.00
csr_bit_bash 1 1 100.00
csrng_csr_bit_bash 13.000s 683.296us 1 1 100.00
csr_aliasing 1 1 100.00
csrng_csr_aliasing 5.000s 87.309us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
csrng_csr_mem_rw_with_rand_reset 3.000s 14.427us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
csrng_csr_rw 2.000s 20.374us 1 1 100.00
csrng_csr_aliasing 5.000s 87.309us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
interrupts 1 1 100.00
csrng_intr 6.000s 291.771us 1 1 100.00
alerts 1 1 100.00
csrng_alert 8.000s 155.205us 1 1 100.00
err 1 1 100.00
csrng_err 2.000s 20.547us 1 1 100.00
cmds 0 1 0.00
csrng_cmds 6.000s 319.764us 0 1 0.00
life cycle 0 1 0.00
csrng_cmds 6.000s 319.764us 0 1 0.00
stress_all 1 1 100.00
csrng_stress_all 59.000s 1478.592us 1 1 100.00
intr_test 1 1 100.00
csrng_intr_test 2.000s 40.165us 1 1 100.00
alert_test 1 1 100.00
csrng_alert_test 2.000s 35.115us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
csrng_tl_errors 4.000s 102.695us 1 1 100.00
tl_d_illegal_access 1 1 100.00
csrng_tl_errors 4.000s 102.695us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
csrng_csr_hw_reset 2.000s 38.867us 1 1 100.00
csrng_csr_rw 2.000s 20.374us 1 1 100.00
csrng_csr_aliasing 5.000s 87.309us 1 1 100.00
csrng_same_csr_outstanding 2.000s 82.806us 1 1 100.00
tl_d_partial_access 4 4 100.00
csrng_csr_hw_reset 2.000s 38.867us 1 1 100.00
csrng_csr_rw 2.000s 20.374us 1 1 100.00
csrng_csr_aliasing 5.000s 87.309us 1 1 100.00
csrng_same_csr_outstanding 2.000s 82.806us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
csrng_sec_cm 4.000s 117.835us 1 1 100.00
csrng_tl_intg_err 6.000s 146.101us 1 1 100.00
sec_cm_config_regwen 1 2 50.00
csrng_regwen 2.000s 3.211us 0 1 0.00
csrng_csr_rw 2.000s 20.374us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
csrng_alert 8.000s 155.205us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
csrng_stress_all 59.000s 1478.592us 1 1 100.00
sec_cm_main_sm_fsm_sparse 3 3 100.00
csrng_intr 6.000s 291.771us 1 1 100.00
csrng_err 2.000s 20.547us 1 1 100.00
csrng_sec_cm 4.000s 117.835us 1 1 100.00
sec_cm_cmd_stage_fsm_sparse 3 3 100.00
csrng_intr 6.000s 291.771us 1 1 100.00
csrng_err 2.000s 20.547us 1 1 100.00
csrng_sec_cm 4.000s 117.835us 1 1 100.00
sec_cm_ctr_drbg_fsm_sparse 3 3 100.00
csrng_intr 6.000s 291.771us 1 1 100.00
csrng_err 2.000s 20.547us 1 1 100.00
csrng_sec_cm 4.000s 117.835us 1 1 100.00
sec_cm_ctr_drbg_ctr_redun 3 3 100.00
csrng_intr 6.000s 291.771us 1 1 100.00
csrng_err 2.000s 20.547us 1 1 100.00
csrng_sec_cm 4.000s 117.835us 1 1 100.00
sec_cm_gen_cmd_ctr_redun 3 3 100.00
csrng_intr 6.000s 291.771us 1 1 100.00
csrng_err 2.000s 20.547us 1 1 100.00
csrng_sec_cm 4.000s 117.835us 1 1 100.00
sec_cm_ctrl_mubi 1 1 100.00
csrng_alert 8.000s 155.205us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
csrng_intr 6.000s 291.771us 1 1 100.00
csrng_err 2.000s 20.547us 1 1 100.00
sec_cm_constants_lc_gated 1 1 100.00
csrng_stress_all 59.000s 1478.592us 1 1 100.00
sec_cm_sw_genbits_bus_consistency 1 1 100.00
csrng_alert 8.000s 155.205us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
csrng_tl_intg_err 6.000s 146.101us 1 1 100.00
sec_cm_aes_cipher_fsm_sparse 3 3 100.00
csrng_intr 6.000s 291.771us 1 1 100.00
csrng_err 2.000s 20.547us 1 1 100.00
csrng_sec_cm 4.000s 117.835us 1 1 100.00
sec_cm_aes_cipher_fsm_redun 2 2 100.00
csrng_intr 6.000s 291.771us 1 1 100.00
csrng_err 2.000s 20.547us 1 1 100.00
sec_cm_aes_cipher_ctrl_sparse 2 2 100.00
csrng_intr 6.000s 291.771us 1 1 100.00
csrng_err 2.000s 20.547us 1 1 100.00
sec_cm_aes_cipher_fsm_local_esc 2 2 100.00
csrng_intr 6.000s 291.771us 1 1 100.00
csrng_err 2.000s 20.547us 1 1 100.00
sec_cm_aes_cipher_ctr_redun 3 3 100.00
csrng_intr 6.000s 291.771us 1 1 100.00
csrng_err 2.000s 20.547us 1 1 100.00
csrng_sec_cm 4.000s 117.835us 1 1 100.00
sec_cm_aes_cipher_data_reg_local_esc 2 2 100.00
csrng_intr 6.000s 291.771us 1 1 100.00
csrng_err 2.000s 20.547us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
csrng_stress_all_with_rand_reset 3602.174s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (csrng_scoreboard.sv:671) [scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (* [*] vs * [*]) 1 test run
csrng_cmds 99479953616139392228695175374046063814452788817406887392956014393125434134585 100
UVM_INFO @ 319764259 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csrng_regwen_vseq.sv:62) virtual_sequencer [csrng_regwen_vseq] Was unable to write INT_STATE_READ_ENABLE 1 test run
csrng_regwen 33591640909052591159702819632427227175416767052696068542036378398592483941716 99
UVM_INFO @ 3210664 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes 1 test run
csrng_stress_all_with_rand_reset 75910230664196174889355233238928258961396527895047318750551492305761335023832 None