Simulation Results: edn/edn0

 
05/08/2026 15:30:30 DVSim: v1.50.0 sha: 023bd59 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 84.51 %
  • code
  • 79.20 %
  • assert
  • 94.36 %
  • func
  • 79.96 %
  • line
  • 96.79 %
  • branch
  • 88.84 %
  • cond
  • 84.74 %
  • toggle
  • 77.78 %
  • FSM
  • 47.85 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.860s 18.626us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.810s 24.898us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.860s 49.581us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 2.970s 148.002us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.540s 69.795us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.160s 73.470us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.860s 49.581us 1 1 100.00
edn_csr_aliasing 1.540s 69.795us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.270s 43.555us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.270s 43.555us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.270s 43.555us 1 1 100.00
interrupts 1 1 100.00
edn_intr 1.070s 21.244us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.060s 94.284us 1 1 100.00
errs 1 1 100.00
edn_err 0.870s 42.106us 1 1 100.00
disable 2 2 100.00
edn_disable 0.810s 41.416us 1 1 100.00
edn_disable_auto_req_mode 1.030s 118.521us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 3.260s 465.283us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.780s 34.464us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 0.910s 41.349us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 2.380s 140.368us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 2.380s 140.368us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.810s 24.898us 1 1 100.00
edn_csr_rw 0.860s 49.581us 1 1 100.00
edn_csr_aliasing 1.540s 69.795us 1 1 100.00
edn_same_csr_outstanding 1.120s 121.616us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.810s 24.898us 1 1 100.00
edn_csr_rw 0.860s 49.581us 1 1 100.00
edn_csr_aliasing 1.540s 69.795us 1 1 100.00
edn_same_csr_outstanding 1.120s 121.616us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 6.840s 1268.516us 1 1 100.00
edn_tl_intg_err 1.910s 207.619us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.920s 40.486us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.060s 94.284us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 6.840s 1268.516us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 6.840s 1268.516us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 6.840s 1268.516us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 6.840s 1268.516us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.060s 94.284us 1 1 100.00
edn_sec_cm 6.840s 1268.516us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.060s 94.284us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.910s 207.619us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 32.680s 3899.706us 1 1 100.00