Simulation Results: edn/edn1

 
05/08/2026 15:30:30 DVSim: v1.50.0 sha: 023bd59 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 86.94 %
  • code
  • 83.00 %
  • assert
  • 97.14 %
  • func
  • 80.67 %
  • line
  • 97.72 %
  • branch
  • 92.21 %
  • cond
  • 90.08 %
  • toggle
  • 94.09 %
  • FSM
  • 40.91 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.760s 55.782us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.920s 13.482us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.780s 16.372us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 1.680s 49.074us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 0.880s 159.091us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.040s 144.509us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.780s 16.372us 1 1 100.00
edn_csr_aliasing 0.880s 159.091us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 0.850s 37.331us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 0.850s 37.331us 1 1 100.00
genbits 1 1 100.00
edn_genbits 0.850s 37.331us 1 1 100.00
interrupts 1 1 100.00
edn_intr 0.840s 24.770us 1 1 100.00
alerts 1 1 100.00
edn_alert 0.910s 25.778us 1 1 100.00
errs 1 1 100.00
edn_err 0.880s 27.171us 1 1 100.00
disable 2 2 100.00
edn_disable 0.750s 14.139us 1 1 100.00
edn_disable_auto_req_mode 0.880s 87.810us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 2.900s 1093.656us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.800s 16.511us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 0.890s 261.273us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 1.380s 50.429us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 1.380s 50.429us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.920s 13.482us 1 1 100.00
edn_csr_rw 0.780s 16.372us 1 1 100.00
edn_csr_aliasing 0.880s 159.091us 1 1 100.00
edn_same_csr_outstanding 0.790s 84.883us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.920s 13.482us 1 1 100.00
edn_csr_rw 0.780s 16.372us 1 1 100.00
edn_csr_aliasing 0.880s 159.091us 1 1 100.00
edn_same_csr_outstanding 0.790s 84.883us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 3.770s 696.680us 1 1 100.00
edn_tl_intg_err 1.830s 98.221us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.790s 54.319us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 0.910s 25.778us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 3.770s 696.680us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 3.770s 696.680us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 3.770s 696.680us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 3.770s 696.680us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 0.910s 25.778us 1 1 100.00
edn_sec_cm 3.770s 696.680us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 0.910s 25.778us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.830s 98.221us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 62.570s 8514.501us 1 1 100.00