Simulation Results: entropy_src/rng_4bits

 
05/08/2026 15:30:30 DVSim: v1.50.0 sha: 023bd59 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 74.41 %
  • code
  • 88.47 %
  • assert
  • 84.24 %
  • func
  • 50.53 %
  • block
  • 94.58 %
  • line
  • 97.21 %
  • branch
  • 86.91 %
  • toggle
  • 75.99 %
  • FSM
  • 93.75 %
Validation stages
V1
83.33%
V2
100.00%
V2S
100.00%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
entropy_src_smoke 2.000s 31.780us 1 1 100.00
csr_hw_reset 1 1 100.00
entropy_src_csr_hw_reset 1.000s 30.091us 1 1 100.00
csr_rw 1 1 100.00
entropy_src_csr_rw 1.000s 167.652us 1 1 100.00
csr_bit_bash 1 1 100.00
entropy_src_csr_bit_bash 11.000s 833.929us 1 1 100.00
csr_aliasing 1 1 100.00
entropy_src_csr_aliasing 3.000s 382.570us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
entropy_src_csr_mem_rw_with_rand_reset 1.000s 12.044us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
entropy_src_csr_rw 1.000s 167.652us 1 1 100.00
entropy_src_csr_aliasing 3.000s 382.570us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 3 3 100.00
entropy_src_smoke 2.000s 31.780us 1 1 100.00
entropy_src_rng 48.000s 14073.013us 1 1 100.00
entropy_src_fw_ov 75.000s 14057.180us 1 1 100.00
firmware_mode 1 1 100.00
entropy_src_fw_ov 75.000s 14057.180us 1 1 100.00
rng_mode 1 1 100.00
entropy_src_rng 48.000s 14073.013us 1 1 100.00
rng_max_rate 1 1 100.00
entropy_src_rng_max_rate 344.000s 13016.400us 1 1 100.00
health_checks 1 1 100.00
entropy_src_rng 48.000s 14073.013us 1 1 100.00
conditioning 1 1 100.00
entropy_src_rng 48.000s 14073.013us 1 1 100.00
interrupts 2 2 100.00
entropy_src_rng 48.000s 14073.013us 1 1 100.00
entropy_src_intr 8.000s 350.992us 1 1 100.00
alerts 2 2 100.00
entropy_src_rng 48.000s 14073.013us 1 1 100.00
entropy_src_functional_alerts 4.000s 2767.375us 1 1 100.00
stress_all 1 1 100.00
entropy_src_stress_all 52.000s 13658.879us 1 1 100.00
functional_errors 1 1 100.00
entropy_src_functional_errors 2.000s 163.117us 1 1 100.00
firmware_ov_read_contiguous_data 1 1 100.00
entropy_src_fw_ov_contiguous 2.000s 32.053us 1 1 100.00
intr_test 1 1 100.00
entropy_src_intr_test 2.000s 29.911us 1 1 100.00
alert_test 1 1 100.00
entropy_src_alert_test 2.000s 42.404us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
entropy_src_tl_errors 3.000s 282.314us 1 1 100.00
tl_d_illegal_access 1 1 100.00
entropy_src_tl_errors 3.000s 282.314us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
entropy_src_csr_hw_reset 1.000s 30.091us 1 1 100.00
entropy_src_csr_rw 1.000s 167.652us 1 1 100.00
entropy_src_csr_aliasing 3.000s 382.570us 1 1 100.00
entropy_src_same_csr_outstanding 2.000s 22.601us 1 1 100.00
tl_d_partial_access 4 4 100.00
entropy_src_csr_hw_reset 1.000s 30.091us 1 1 100.00
entropy_src_csr_rw 1.000s 167.652us 1 1 100.00
entropy_src_csr_aliasing 3.000s 382.570us 1 1 100.00
entropy_src_same_csr_outstanding 2.000s 22.601us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
entropy_src_sec_cm 2.000s 345.834us 1 1 100.00
entropy_src_tl_intg_err 2.000s 97.006us 1 1 100.00
sec_cm_config_regwen 2 2 100.00
entropy_src_rng 48.000s 14073.013us 1 1 100.00
entropy_src_cfg_regwen 2.000s 25.132us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
entropy_src_rng 48.000s 14073.013us 1 1 100.00
sec_cm_config_redun 1 1 100.00
entropy_src_rng 48.000s 14073.013us 1 1 100.00
sec_cm_intersig_mubi 2 2 100.00
entropy_src_rng 48.000s 14073.013us 1 1 100.00
entropy_src_fw_ov 75.000s 14057.180us 1 1 100.00
sec_cm_main_sm_fsm_sparse 2 2 100.00
entropy_src_functional_errors 2.000s 163.117us 1 1 100.00
entropy_src_sec_cm 2.000s 345.834us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 2 2 100.00
entropy_src_functional_errors 2.000s 163.117us 1 1 100.00
entropy_src_sec_cm 2.000s 345.834us 1 1 100.00
sec_cm_rng_bkgn_chk 1 1 100.00
entropy_src_rng 48.000s 14073.013us 1 1 100.00
sec_cm_fifo_ctr_redun 2 2 100.00
entropy_src_functional_errors 2.000s 163.117us 1 1 100.00
entropy_src_sec_cm 2.000s 345.834us 1 1 100.00
sec_cm_ctr_redun 2 2 100.00
entropy_src_functional_errors 2.000s 163.117us 1 1 100.00
entropy_src_sec_cm 2.000s 345.834us 1 1 100.00
sec_cm_ctr_local_esc 1 1 100.00
entropy_src_functional_errors 2.000s 163.117us 1 1 100.00
sec_cm_esfinal_rdata_bus_consistency 1 1 100.00
entropy_src_functional_alerts 4.000s 2767.375us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
entropy_src_tl_intg_err 2.000s 97.006us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
external_health_tests 1 1 100.00
entropy_src_rng_with_xht_rsps 188.000s 13063.253us 1 1 100.00
stress_all_with_rand_reset 0 1 0.00
entropy_src_stress_all_with_rand_reset 1.000s 8.528us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (entropy_src_base_vseq.sv:83) virtual_sequencer [mirror] Failed to mirror repcnts_total_fails 1 test run
entropy_src_stress_all_with_rand_reset 3614188661448570181147500017009020118603065956823937939195609395760990142575 112
UVM_INFO @ 8528310 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (entropy_src_base_vseq.sv:83) virtual_sequencer [mirror] Failed to mirror adaptp_hi_total_fails 1 test run
entropy_src_csr_mem_rw_with_rand_reset 31519862594575453574512151730508388401774270114092940192629173909979985186353 113
UVM_INFO @ 12043775 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---