Simulation Results: flash_ctrl

 
05/08/2026 15:30:30 DVSim: v1.50.0 sha: 023bd59 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.40 %
  • code
  • 93.77 %
  • assert
  • 97.02 %
  • func
  • 95.42 %
  • line
  • 95.96 %
  • branch
  • 97.06 %
  • cond
  • 93.86 %
  • toggle
  • 95.60 %
  • FSM
  • 86.39 %
Validation stages
V1
100.00%
V2
100.00%
V2S
95.83%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
flash_ctrl_smoke 69.620s 29.827us 1 1 100.00
smoke_hw 1 1 100.00
flash_ctrl_smoke_hw 12.500s 80.165us 1 1 100.00
csr_hw_reset 1 1 100.00
flash_ctrl_csr_hw_reset 24.200s 48.956us 1 1 100.00
csr_rw 1 1 100.00
flash_ctrl_csr_rw 8.410s 157.785us 1 1 100.00
csr_bit_bash 1 1 100.00
flash_ctrl_csr_bit_bash 51.160s 8141.857us 1 1 100.00
csr_aliasing 1 1 100.00
flash_ctrl_csr_aliasing 41.710s 3145.737us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
flash_ctrl_csr_mem_rw_with_rand_reset 8.670s 342.617us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
flash_ctrl_csr_rw 8.410s 157.785us 1 1 100.00
flash_ctrl_csr_aliasing 41.710s 3145.737us 1 1 100.00
mem_walk 1 1 100.00
flash_ctrl_mem_walk 6.170s 30.271us 1 1 100.00
mem_partial_access 1 1 100.00
flash_ctrl_mem_partial_access 6.200s 19.458us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sw_op 1 1 100.00
flash_ctrl_sw_op 11.940s 31.179us 1 1 100.00
host_read_direct 1 1 100.00
flash_ctrl_host_dir_rd 23.710s 147.633us 1 1 100.00
rma_hw_if 3 3 100.00
flash_ctrl_hw_rma 1241.770s 364532.335us 1 1 100.00
flash_ctrl_hw_rma_reset 528.740s 80155.396us 1 1 100.00
flash_ctrl_lcmgr_intg 8.080s 26.049us 1 1 100.00
host_controller_arb 1 1 100.00
flash_ctrl_host_ctrl_arb 1350.370s 296025.617us 1 1 100.00
erase_suspend 1 1 100.00
flash_ctrl_erase_suspend 273.200s 9315.386us 1 1 100.00
program_reset 1 1 100.00
flash_ctrl_prog_reset 6.330s 28.083us 1 1 100.00
full_memory_access 1 1 100.00
flash_ctrl_full_mem_access 1903.940s 215213.388us 1 1 100.00
rd_buff_eviction 1 1 100.00
flash_ctrl_rd_buff_evict 49.190s 765.760us 1 1 100.00
rd_buff_eviction_w_ecc 3 3 100.00
flash_ctrl_rw_evict 13.820s 54.209us 1 1 100.00
flash_ctrl_rw_evict_all_en 21.440s 31.980us 1 1 100.00
flash_ctrl_re_evict 19.890s 129.511us 1 1 100.00
host_arb 1 1 100.00
flash_ctrl_phy_arb 19.260s 52.730us 1 1 100.00
host_interleave 1 1 100.00
flash_ctrl_phy_arb 19.260s 52.730us 1 1 100.00
memory_protection 1 1 100.00
flash_ctrl_mp_regions 152.900s 46210.982us 1 1 100.00
fetch_code 1 1 100.00
flash_ctrl_fetch_code 15.630s 8652.178us 1 1 100.00
all_partitions 1 1 100.00
flash_ctrl_rand_ops 116.490s 192.018us 1 1 100.00
error_mp 1 1 100.00
flash_ctrl_error_mp 416.560s 7474.653us 1 1 100.00
error_prog_win 1 1 100.00
flash_ctrl_error_prog_win 381.410s 915.163us 1 1 100.00
error_prog_type 1 1 100.00
flash_ctrl_error_prog_type 855.660s 875.470us 1 1 100.00
error_read_seed 1 1 100.00
flash_ctrl_hw_read_seed_err 6.300s 23.035us 1 1 100.00
read_write_overflow 1 1 100.00
flash_ctrl_oversize_error 127.200s 15110.886us 1 1 100.00
flash_ctrl_disable 1 1 100.00
flash_ctrl_disable 10.430s 19.050us 1 1 100.00
flash_ctrl_connect 1 1 100.00
flash_ctrl_connect 6.270s 16.513us 1 1 100.00
stress_all 1 1 100.00
flash_ctrl_stress_all 429.550s 490.634us 1 1 100.00
secret_partition 2 2 100.00
flash_ctrl_hw_sec_otp 141.770s 6961.969us 1 1 100.00
flash_ctrl_otp_reset 61.110s 41.968us 1 1 100.00
isolation_partition 1 1 100.00
flash_ctrl_hw_rma 1241.770s 364532.335us 1 1 100.00
interrupts 4 4 100.00
flash_ctrl_intr_rd 98.670s 2396.890us 1 1 100.00
flash_ctrl_intr_wr 47.870s 2726.824us 1 1 100.00
flash_ctrl_intr_rd_slow_flash 185.400s 46924.725us 1 1 100.00
flash_ctrl_intr_wr_slow_flash 140.630s 101320.079us 1 1 100.00
invalid_op 1 1 100.00
flash_ctrl_invalid_op 40.690s 2113.431us 1 1 100.00
mid_op_rst 1 1 100.00
flash_ctrl_mid_op_rst 43.940s 1990.328us 1 1 100.00
double_bit_err 5 5 100.00
flash_ctrl_read_word_sweep_derr 11.080s 109.672us 1 1 100.00
flash_ctrl_ro_derr 110.560s 1691.462us 1 1 100.00
flash_ctrl_rw_derr 170.890s 7471.783us 1 1 100.00
flash_ctrl_derr_detect 102.650s 3022.563us 1 1 100.00
flash_ctrl_integrity 346.790s 4500.798us 1 1 100.00
single_bit_err 3 3 100.00
flash_ctrl_read_word_sweep_serr 10.100s 109.897us 1 1 100.00
flash_ctrl_ro_serr 90.870s 3344.937us 1 1 100.00
flash_ctrl_rw_serr 155.370s 2373.914us 1 1 100.00
singlebit_err_counter 1 1 100.00
flash_ctrl_serr_counter 60.260s 9752.574us 1 1 100.00
singlebit_err_address 1 1 100.00
flash_ctrl_serr_address 42.600s 1363.291us 1 1 100.00
scramble 5 5 100.00
flash_ctrl_wo 156.040s 42503.274us 1 1 100.00
flash_ctrl_write_word_sweep 9.400s 160.618us 1 1 100.00
flash_ctrl_read_word_sweep 8.860s 29.796us 1 1 100.00
flash_ctrl_ro 85.010s 1868.411us 1 1 100.00
flash_ctrl_rw 345.520s 4295.760us 1 1 100.00
filesystem_support 1 1 100.00
flash_ctrl_fs_sup 23.240s 547.274us 1 1 100.00
rma_write_process_error 2 2 100.00
flash_ctrl_rma_err 569.650s 161074.099us 1 1 100.00
flash_ctrl_hw_prog_rma_wipe_err 63.350s 10021.222us 1 1 100.00
alert_test 1 1 100.00
flash_ctrl_alert_test 7.890s 161.618us 1 1 100.00
intr_test 1 1 100.00
flash_ctrl_intr_test 8.790s 57.532us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
flash_ctrl_tl_errors 11.890s 196.160us 1 1 100.00
tl_d_illegal_access 1 1 100.00
flash_ctrl_tl_errors 11.890s 196.160us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
flash_ctrl_csr_hw_reset 24.200s 48.956us 1 1 100.00
flash_ctrl_csr_rw 8.410s 157.785us 1 1 100.00
flash_ctrl_csr_aliasing 41.710s 3145.737us 1 1 100.00
flash_ctrl_same_csr_outstanding 16.990s 255.512us 1 1 100.00
tl_d_partial_access 4 4 100.00
flash_ctrl_csr_hw_reset 24.200s 48.956us 1 1 100.00
flash_ctrl_csr_rw 8.410s 157.785us 1 1 100.00
flash_ctrl_csr_aliasing 41.710s 3145.737us 1 1 100.00
flash_ctrl_same_csr_outstanding 16.990s 255.512us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
flash_ctrl_shadow_reg_errors 27.480s 49.808us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
flash_ctrl_shadow_reg_errors 27.480s 49.808us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
flash_ctrl_shadow_reg_errors 27.480s 49.808us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
flash_ctrl_shadow_reg_errors 27.480s 49.808us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
flash_ctrl_shadow_reg_errors_with_csr_rw 20.240s 323.375us 1 1 100.00
tl_intg_err 2 2 100.00
flash_ctrl_sec_cm 1814.030s 1765.649us 1 1 100.00
flash_ctrl_tl_intg_err 166.170s 1980.596us 1 1 100.00
sec_cm_reg_bus_integrity 1 1 100.00
flash_ctrl_tl_intg_err 166.170s 1980.596us 1 1 100.00
sec_cm_host_bus_integrity 1 1 100.00
flash_ctrl_tl_intg_err 166.170s 1980.596us 1 1 100.00
sec_cm_mem_bus_integrity 2 2 100.00
flash_ctrl_rd_intg 15.470s 72.562us 1 1 100.00
flash_ctrl_wr_intg 6.960s 49.318us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
flash_ctrl_smoke 69.620s 29.827us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 4 4 100.00
flash_ctrl_otp_reset 61.110s 41.968us 1 1 100.00
flash_ctrl_disable 10.430s 19.050us 1 1 100.00
flash_ctrl_sec_info_access 41.020s 5948.530us 1 1 100.00
flash_ctrl_connect 6.270s 16.513us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
flash_ctrl_config_regwen 6.370s 47.752us 1 1 100.00
sec_cm_data_regions_config_regwen 1 1 100.00
flash_ctrl_csr_rw 8.410s 157.785us 1 1 100.00
sec_cm_data_regions_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 27.480s 49.808us 1 1 100.00
sec_cm_info_regions_config_regwen 1 1 100.00
flash_ctrl_csr_rw 8.410s 157.785us 1 1 100.00
sec_cm_info_regions_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 27.480s 49.808us 1 1 100.00
sec_cm_bank_config_regwen 1 1 100.00
flash_ctrl_csr_rw 8.410s 157.785us 1 1 100.00
sec_cm_bank_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 27.480s 49.808us 1 1 100.00
sec_cm_mem_ctrl_global_esc 1 1 100.00
flash_ctrl_disable 10.430s 19.050us 1 1 100.00
sec_cm_mem_ctrl_local_esc 2 2 100.00
flash_ctrl_rd_intg 15.470s 72.562us 1 1 100.00
flash_ctrl_access_after_disable 6.900s 44.892us 1 1 100.00
sec_cm_mem_addr_infection 1 1 100.00
flash_ctrl_host_addr_infection 14.370s 55.740us 1 1 100.00
sec_cm_mem_disable_config_mubi 1 1 100.00
flash_ctrl_disable 10.430s 19.050us 1 1 100.00
sec_cm_exec_config_redun 1 1 100.00
flash_ctrl_fetch_code 15.630s 8652.178us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
flash_ctrl_rw 345.520s 4295.760us 1 1 100.00
sec_cm_mem_integrity 3 3 100.00
flash_ctrl_rw_serr 155.370s 2373.914us 1 1 100.00
flash_ctrl_rw_derr 170.890s 7471.783us 1 1 100.00
flash_ctrl_integrity 346.790s 4500.798us 1 1 100.00
sec_cm_rma_entry_mem_sec_wipe 1 1 100.00
flash_ctrl_hw_rma 1241.770s 364532.335us 1 1 100.00
sec_cm_ctrl_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1814.030s 1765.649us 1 1 100.00
sec_cm_phy_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1814.030s 1765.649us 1 1 100.00
sec_cm_phy_prog_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1814.030s 1765.649us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
flash_ctrl_sec_cm 1814.030s 1765.649us 1 1 100.00
sec_cm_phy_arbiter_ctrl_redun 1 1 100.00
flash_ctrl_phy_arb_redun 11.760s 843.987us 1 1 100.00
sec_cm_phy_host_grant_ctrl_consistency 0 1 0.00
flash_ctrl_phy_host_grant_err 6.100s 6.499us 0 1 0.00
sec_cm_phy_ack_ctrl_consistency 1 1 100.00
flash_ctrl_phy_ack_consistency 6.350s 81.252us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
flash_ctrl_sec_cm 1814.030s 1765.649us 1 1 100.00
sec_cm_mem_tl_lc_gate_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1814.030s 1765.649us 1 1 100.00
sec_cm_prog_tl_lc_gate_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1814.030s 1765.649us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
asymmetric_read_path 1 1 100.00
flash_ctrl_rd_ooo 25.150s 77.041us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
flash_ctrl_basic_rw 378.550s 6278.474us 1 1 100.00

Error Messages

   Test seed line log context
Offending '(!$isunknown((alert_tx.alert_p ^ alert_tx.alert_n)))' 1 test run
flash_ctrl_phy_host_grant_err 66246903566730476554171908197808819988147864883675528485336631883641802721452 125
UVM_ERROR @ 6498.6 ns: (alert_esc_if.sv:211) [ASSERT FAILED] AlertKnown_A
UVM_INFO @ 6498.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---