Simulation Results: hmac

 
05/08/2026 15:30:30 DVSim: v1.50.0 sha: 023bd59 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 79.68 %
  • code
  • 97.49 %
  • assert
  • 97.60 %
  • func
  • 43.96 %
  • line
  • 99.59 %
  • branch
  • 98.68 %
  • cond
  • 95.06 %
  • toggle
  • 100.00 %
  • FSM
  • 94.12 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
hmac_smoke 8.210s 656.118us 1 1 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 0.800s 35.129us 1 1 100.00
csr_rw 1 1 100.00
hmac_csr_rw 0.770s 20.683us 1 1 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 8.360s 1158.827us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 4.340s 330.338us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 1.650s 171.557us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
hmac_csr_rw 0.770s 20.683us 1 1 100.00
hmac_csr_aliasing 4.340s 330.338us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 1 1 100.00
hmac_long_msg 70.340s 5751.893us 1 1 100.00
back_pressure 1 1 100.00
hmac_back_pressure 15.240s 993.682us 1 1 100.00
test_vectors 6 6 100.00
hmac_test_sha256_vectors 176.710s 7209.214us 1 1 100.00
hmac_test_sha384_vectors 19.990s 614.215us 1 1 100.00
hmac_test_sha512_vectors 386.020s 16686.636us 1 1 100.00
hmac_test_hmac256_vectors 10.730s 951.012us 1 1 100.00
hmac_test_hmac384_vectors 11.920s 1017.779us 1 1 100.00
hmac_test_hmac512_vectors 12.330s 1126.503us 1 1 100.00
burst_wr 1 1 100.00
hmac_burst_wr 1.320s 487.927us 1 1 100.00
datapath_stress 1 1 100.00
hmac_datapath_stress 504.460s 17534.478us 1 1 100.00
error 1 1 100.00
hmac_error 56.980s 3624.669us 1 1 100.00
wipe_secret 1 1 100.00
hmac_wipe_secret 7.470s 903.783us 1 1 100.00
save_and_restore 6 6 100.00
hmac_smoke 8.210s 656.118us 1 1 100.00
hmac_long_msg 70.340s 5751.893us 1 1 100.00
hmac_back_pressure 15.240s 993.682us 1 1 100.00
hmac_datapath_stress 504.460s 17534.478us 1 1 100.00
hmac_burst_wr 1.320s 487.927us 1 1 100.00
hmac_stress_all 80.910s 43175.691us 1 1 100.00
fifo_empty_status_interrupt 11 11 100.00
hmac_smoke 8.210s 656.118us 1 1 100.00
hmac_long_msg 70.340s 5751.893us 1 1 100.00
hmac_back_pressure 15.240s 993.682us 1 1 100.00
hmac_datapath_stress 504.460s 17534.478us 1 1 100.00
hmac_wipe_secret 7.470s 903.783us 1 1 100.00
hmac_test_sha256_vectors 176.710s 7209.214us 1 1 100.00
hmac_test_sha384_vectors 19.990s 614.215us 1 1 100.00
hmac_test_sha512_vectors 386.020s 16686.636us 1 1 100.00
hmac_test_hmac256_vectors 10.730s 951.012us 1 1 100.00
hmac_test_hmac384_vectors 11.920s 1017.779us 1 1 100.00
hmac_test_hmac512_vectors 12.330s 1126.503us 1 1 100.00
wide_digest_configurable_key_length 14 14 100.00
hmac_smoke 8.210s 656.118us 1 1 100.00
hmac_long_msg 70.340s 5751.893us 1 1 100.00
hmac_back_pressure 15.240s 993.682us 1 1 100.00
hmac_datapath_stress 504.460s 17534.478us 1 1 100.00
hmac_burst_wr 1.320s 487.927us 1 1 100.00
hmac_error 56.980s 3624.669us 1 1 100.00
hmac_wipe_secret 7.470s 903.783us 1 1 100.00
hmac_test_sha256_vectors 176.710s 7209.214us 1 1 100.00
hmac_test_sha384_vectors 19.990s 614.215us 1 1 100.00
hmac_test_sha512_vectors 386.020s 16686.636us 1 1 100.00
hmac_test_hmac256_vectors 10.730s 951.012us 1 1 100.00
hmac_test_hmac384_vectors 11.920s 1017.779us 1 1 100.00
hmac_test_hmac512_vectors 12.330s 1126.503us 1 1 100.00
hmac_stress_all 80.910s 43175.691us 1 1 100.00
stress_all 1 1 100.00
hmac_stress_all 80.910s 43175.691us 1 1 100.00
alert_test 1 1 100.00
hmac_alert_test 0.680s 24.222us 1 1 100.00
intr_test 1 1 100.00
hmac_intr_test 0.600s 46.977us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
hmac_tl_errors 2.270s 448.362us 1 1 100.00
tl_d_illegal_access 1 1 100.00
hmac_tl_errors 2.270s 448.362us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
hmac_csr_hw_reset 0.800s 35.129us 1 1 100.00
hmac_csr_rw 0.770s 20.683us 1 1 100.00
hmac_csr_aliasing 4.340s 330.338us 1 1 100.00
hmac_same_csr_outstanding 2.030s 132.031us 1 1 100.00
tl_d_partial_access 4 4 100.00
hmac_csr_hw_reset 0.800s 35.129us 1 1 100.00
hmac_csr_rw 0.770s 20.683us 1 1 100.00
hmac_csr_aliasing 4.340s 330.338us 1 1 100.00
hmac_same_csr_outstanding 2.030s 132.031us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
hmac_sec_cm 0.940s 97.621us 1 1 100.00
hmac_tl_intg_err 3.280s 274.509us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
hmac_tl_intg_err 3.280s 274.509us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 1 1 100.00
hmac_smoke 8.210s 656.118us 1 1 100.00
stress_reset 1 1 100.00
hmac_stress_reset 1.770s 79.778us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
hmac_stress_all_with_rand_reset 49.730s 9002.305us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 2.030s 86.460us 1 1 100.00