Simulation Results: i2c

 
05/08/2026 15:30:30 DVSim: v1.50.0 sha: 023bd59 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 86.74 %
  • code
  • 78.94 %
  • assert
  • 96.83 %
  • func
  • 84.46 %
  • line
  • 96.63 %
  • branch
  • 92.90 %
  • cond
  • 87.07 %
  • toggle
  • 74.04 %
  • FSM
  • 44.05 %
Validation stages
V1
100.00%
V2
87.80%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
host_smoke 1 1 100.00
i2c_host_smoke 14.150s 1495.720us 1 1 100.00
target_smoke 1 1 100.00
i2c_target_smoke 8.870s 4257.433us 1 1 100.00
csr_hw_reset 1 1 100.00
i2c_csr_hw_reset 0.880s 21.213us 1 1 100.00
csr_rw 1 1 100.00
i2c_csr_rw 0.810s 47.361us 1 1 100.00
csr_bit_bash 1 1 100.00
i2c_csr_bit_bash 3.710s 666.461us 1 1 100.00
csr_aliasing 1 1 100.00
i2c_csr_aliasing 1.150s 169.096us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
i2c_csr_mem_rw_with_rand_reset 0.950s 42.563us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
i2c_csr_rw 0.810s 47.361us 1 1 100.00
i2c_csr_aliasing 1.150s 169.096us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
host_error_intr 0 1 0.00
i2c_host_error_intr 0.710s 9.541us 0 1 0.00
host_stress_all 1 1 100.00
i2c_host_stress_all 543.540s 111694.247us 1 1 100.00
host_maxperf 1 1 100.00
i2c_host_perf 2.040s 363.532us 1 1 100.00
host_override 1 1 100.00
i2c_host_override 0.760s 36.141us 1 1 100.00
host_fifo_watermark 1 1 100.00
i2c_host_fifo_watermark 173.430s 10289.741us 1 1 100.00
host_fifo_overflow 1 1 100.00
i2c_host_fifo_overflow 38.230s 2211.972us 1 1 100.00
host_fifo_reset 3 3 100.00
i2c_host_fifo_reset_fmt 0.930s 352.497us 1 1 100.00
i2c_host_fifo_fmt_empty 4.570s 432.816us 1 1 100.00
i2c_host_fifo_reset_rx 2.270s 662.275us 1 1 100.00
host_fifo_full 1 1 100.00
i2c_host_fifo_full 23.430s 1863.728us 1 1 100.00
host_timeout 1 1 100.00
i2c_host_stretch_timeout 6.510s 2377.166us 1 1 100.00
i2c_host_mode_toggle 0 1 0.00
i2c_host_mode_toggle 0.980s 42.257us 0 1 0.00
target_glitch 0 1 0.00
i2c_target_glitch 1.860s 2821.432us 0 1 0.00
target_stress_all 1 1 100.00
i2c_target_stress_all 52.920s 45997.621us 1 1 100.00
target_maxperf 1 1 100.00
i2c_target_perf 4.170s 2092.777us 1 1 100.00
target_fifo_empty 2 2 100.00
i2c_target_stress_rd 44.510s 6109.213us 1 1 100.00
i2c_target_intr_smoke 5.030s 5151.765us 1 1 100.00
target_fifo_reset 2 2 100.00
i2c_target_fifo_reset_acq 1.320s 187.820us 1 1 100.00
i2c_target_fifo_reset_tx 1.260s 310.927us 1 1 100.00
target_fifo_full 3 3 100.00
i2c_target_stress_wr 22.510s 18615.721us 1 1 100.00
i2c_target_stress_rd 44.510s 6109.213us 1 1 100.00
i2c_target_intr_stress_wr 13.790s 16203.805us 1 1 100.00
target_timeout 1 1 100.00
i2c_target_timeout 5.100s 5602.933us 1 1 100.00
target_clock_stretch 0 1 0.00
i2c_target_stretch 2.200s 10092.479us 0 1 0.00
bad_address 1 1 100.00
i2c_target_bad_addr 4.240s 3094.072us 1 1 100.00
target_mode_glitch 0 1 0.00
i2c_target_hrst 5.330s 10728.360us 0 1 0.00
target_fifo_watermark 2 2 100.00
i2c_target_fifo_watermarks_acq 1.440s 2442.589us 1 1 100.00
i2c_target_fifo_watermarks_tx 1.100s 162.999us 1 1 100.00
host_mode_config_perf 2 2 100.00
i2c_host_perf 2.040s 363.532us 1 1 100.00
i2c_host_perf_precise 8.910s 1311.919us 1 1 100.00
host_mode_clock_stretching 1 1 100.00
i2c_host_stretch_timeout 6.510s 2377.166us 1 1 100.00
target_mode_tx_stretch_ctrl 1 1 100.00
i2c_target_tx_stretch_ctrl 2.020s 119.340us 1 1 100.00
target_mode_nack_generation 3 3 100.00
i2c_target_nack_acqfull 2.490s 2387.255us 1 1 100.00
i2c_target_nack_acqfull_addr 2.530s 502.821us 1 1 100.00
i2c_target_nack_txstretch 1.560s 787.673us 1 1 100.00
host_mode_halt_on_nak 1 1 100.00
i2c_host_may_nack 3.160s 1810.790us 1 1 100.00
target_mode_smbus_maxlen 1 1 100.00
i2c_target_smbus_maxlen 1.770s 5307.120us 1 1 100.00
alert_test 1 1 100.00
i2c_alert_test 0.670s 47.546us 1 1 100.00
intr_test 1 1 100.00
i2c_intr_test 0.660s 29.580us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
i2c_tl_errors 1.800s 394.621us 1 1 100.00
tl_d_illegal_access 1 1 100.00
i2c_tl_errors 1.800s 394.621us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
i2c_csr_hw_reset 0.880s 21.213us 1 1 100.00
i2c_csr_rw 0.810s 47.361us 1 1 100.00
i2c_csr_aliasing 1.150s 169.096us 1 1 100.00
i2c_same_csr_outstanding 0.870s 39.347us 1 1 100.00
tl_d_partial_access 4 4 100.00
i2c_csr_hw_reset 0.880s 21.213us 1 1 100.00
i2c_csr_rw 0.810s 47.361us 1 1 100.00
i2c_csr_aliasing 1.150s 169.096us 1 1 100.00
i2c_same_csr_outstanding 0.870s 39.347us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
i2c_tl_intg_err 1.920s 514.474us 1 1 100.00
i2c_sec_cm 0.770s 512.458us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
i2c_tl_intg_err 1.920s 514.474us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
host_stress_all_with_rand_reset 0 1 0.00
i2c_host_stress_all_with_rand_reset 15.730s 4374.497us 0 1 0.00
target_error_intr 0 1 0.00
i2c_target_unexp_stop 1.420s 260.541us 0 1 0.00
target_stress_all_with_rand_reset 0 1 0.00
i2c_target_stress_all_with_rand_reset 4.920s 1675.328us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1286) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 2 test runs
i2c_host_stress_all_with_rand_reset 65646853010176224961500644088141817878714547952841288247458101316877545945858 102
UVM_INFO @ 4374497321 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
i2c_target_stress_all_with_rand_reset 61428694483687665467761335818030905248871976492516912572637665446990501596851 85
UVM_INFO @ 1675328038 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between 1 test run
i2c_host_error_intr 92840296274870702471429972113076926353272389682875916133586459461468144674190 80
UVM_INFO @ 9540967 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between 1 test run
i2c_target_glitch 11996215404401603168618078343409564230152542664761274005775116857710515471495 84
UVM_INFO @ 2821432203 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred! 1 test run
i2c_target_stretch 58070751769768995985549990881581243852324170720134336609771184745929266906891 78
UVM_INFO @ 10092478756 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) 1 test run
i2c_target_unexp_stop 72483628009954222870455079449686399514372227415662935306755590421800268409993 78
UVM_INFO @ 260540651 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! 1 test run
i2c_target_hrst 63915771800151300397553954864499917261984076393475220479631762981044240794855 79
UVM_INFO @ 10728359507 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:627) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpRead 1 test run
i2c_host_mode_toggle 16644243861868154788027035391079722634399940551162116548035374170142561441818 87
--> EXP:
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