Simulation Results: lc_ctrl/volatile_unlock_disabled

 
05/08/2026 15:30:30 DVSim: v1.50.0 sha: 023bd59 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 90.25 %
  • code
  • 83.59 %
  • assert
  • 94.69 %
  • func
  • 92.47 %
  • line
  • 97.20 %
  • branch
  • 93.70 %
  • cond
  • 78.87 %
  • toggle
  • 86.51 %
  • FSM
  • 61.68 %
Validation stages
V1
100.00%
V2
96.67%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 1.260s 28.796us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 0.980s 96.839us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 0.940s 23.930us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.500s 35.469us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.510s 79.416us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.190s 103.138us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 0.940s 23.930us 1 1 100.00
lc_ctrl_csr_aliasing 1.510s 79.416us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 4.100s 82.996us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 5.360s 1577.554us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 1.120s 38.576us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 2.330s 121.549us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 7.570s 1097.782us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 7.640s 1639.321us 1 1 100.00
security_escalation 6 7 85.71
lc_ctrl_state_failure 7.570s 1097.782us 1 1 100.00
lc_ctrl_prog_failure 2.330s 121.549us 1 1 100.00
lc_ctrl_errors 7.640s 1639.321us 1 1 100.00
lc_ctrl_security_escalation 4.120s 1004.913us 1 1 100.00
lc_ctrl_jtag_state_failure 14.960s 8674.744us 1 1 100.00
lc_ctrl_jtag_prog_failure 8.700s 3485.327us 1 1 100.00
lc_ctrl_jtag_errors 15.630s 3017.800us 0 1 0.00
jtag_access 12 13 92.31
lc_ctrl_jtag_smoke 5.490s 1958.010us 1 1 100.00
lc_ctrl_jtag_state_post_trans 7.090s 822.018us 1 1 100.00
lc_ctrl_jtag_prog_failure 8.700s 3485.327us 1 1 100.00
lc_ctrl_jtag_errors 15.630s 3017.800us 0 1 0.00
lc_ctrl_jtag_access 3.530s 1020.034us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 12.230s 8635.448us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 1.370s 1051.814us 1 1 100.00
lc_ctrl_jtag_csr_rw 1.790s 175.597us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 4.590s 672.415us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 7.440s 3808.692us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.380s 103.573us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 2.450s 595.154us 1 1 100.00
lc_ctrl_jtag_alert_test 1.580s 64.713us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 3.830s 2931.674us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 0.810s 26.145us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 354.670s 64249.867us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 1.020s 195.794us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 1.470s 22.909us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 1.470s 22.909us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.980s 96.839us 1 1 100.00
lc_ctrl_csr_rw 0.940s 23.930us 1 1 100.00
lc_ctrl_csr_aliasing 1.510s 79.416us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.510s 24.371us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.980s 96.839us 1 1 100.00
lc_ctrl_csr_rw 0.940s 23.930us 1 1 100.00
lc_ctrl_csr_aliasing 1.510s 79.416us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.510s 24.371us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 7.230s 1002.339us 1 1 100.00
lc_ctrl_tl_intg_err 1.100s 92.159us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 1.100s 92.159us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 5.360s 1577.554us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 7.570s 1097.782us 1 1 100.00
lc_ctrl_sec_cm 7.230s 1002.339us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 7.570s 1097.782us 1 1 100.00
lc_ctrl_sec_cm 7.230s 1002.339us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 7.570s 1097.782us 1 1 100.00
lc_ctrl_sec_cm 7.230s 1002.339us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 7.570s 1097.782us 1 1 100.00
lc_ctrl_sec_cm 7.230s 1002.339us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 7.570s 1097.782us 1 1 100.00
lc_ctrl_sec_cm 7.230s 1002.339us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 7.570s 1097.782us 1 1 100.00
lc_ctrl_sec_cm 7.230s 1002.339us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 7.570s 1097.782us 1 1 100.00
lc_ctrl_sec_cm 7.230s 1002.339us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 7.570s 1097.782us 1 1 100.00
lc_ctrl_sec_cm 7.230s 1002.339us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 4.120s 1004.913us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 4.100s 82.996us 1 1 100.00
lc_ctrl_jtag_state_post_trans 7.090s 822.018us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 5.950s 334.749us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 5.950s 334.749us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 4.260s 453.668us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 5.140s 313.350us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 5.140s 313.350us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 38.750s 2509.624us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (* [*] vs * [*]) 1 test run
lc_ctrl_jtag_errors 16600056157054984842262386601665925820802354126320922043778613494697525099084 3112
UVM_INFO @ 3017800343 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1286) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
lc_ctrl_stress_all_with_rand_reset 59531897190439039036550462421377920160138283242944548166710406518891021983330 889
UVM_INFO @ 2509623764 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---