Simulation Results: lc_ctrl/volatile_unlock_enabled

 
05/08/2026 15:30:30 DVSim: v1.50.0 sha: 023bd59 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 90.78 %
  • code
  • 84.10 %
  • assert
  • 94.69 %
  • func
  • 93.55 %
  • line
  • 97.22 %
  • branch
  • 93.66 %
  • cond
  • 79.61 %
  • toggle
  • 86.45 %
  • FSM
  • 63.55 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 1.200s 92.764us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 0.840s 64.105us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 0.870s 19.111us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.640s 295.136us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.020s 49.519us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 0.910s 42.909us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 0.870s 19.111us 1 1 100.00
lc_ctrl_csr_aliasing 1.020s 49.519us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 3.880s 101.567us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 6.380s 195.782us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 0.710s 54.004us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 1.740s 48.750us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 8.050s 4398.465us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 4.630s 1263.707us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 8.050s 4398.465us 1 1 100.00
lc_ctrl_prog_failure 1.740s 48.750us 1 1 100.00
lc_ctrl_errors 4.630s 1263.707us 1 1 100.00
lc_ctrl_security_escalation 4.280s 1100.611us 1 1 100.00
lc_ctrl_jtag_state_failure 18.190s 1576.690us 1 1 100.00
lc_ctrl_jtag_prog_failure 2.660s 314.175us 1 1 100.00
lc_ctrl_jtag_errors 13.740s 5824.619us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 2.640s 449.617us 1 1 100.00
lc_ctrl_jtag_state_post_trans 6.420s 328.281us 1 1 100.00
lc_ctrl_jtag_prog_failure 2.660s 314.175us 1 1 100.00
lc_ctrl_jtag_errors 13.740s 5824.619us 1 1 100.00
lc_ctrl_jtag_access 1.520s 372.174us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 8.990s 3936.984us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 2.130s 116.793us 1 1 100.00
lc_ctrl_jtag_csr_rw 0.910s 61.472us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 4.250s 1077.391us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 4.080s 1772.245us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 0.980s 139.667us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 1.720s 1318.870us 1 1 100.00
lc_ctrl_jtag_alert_test 0.940s 195.852us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 4.160s 1684.257us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 0.890s 25.322us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 51.010s 88516.906us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 0.810s 20.438us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 1.910s 174.449us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 1.910s 174.449us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.840s 64.105us 1 1 100.00
lc_ctrl_csr_rw 0.870s 19.111us 1 1 100.00
lc_ctrl_csr_aliasing 1.020s 49.519us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.070s 32.667us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.840s 64.105us 1 1 100.00
lc_ctrl_csr_rw 0.870s 19.111us 1 1 100.00
lc_ctrl_csr_aliasing 1.020s 49.519us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.070s 32.667us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 5.910s 146.560us 1 1 100.00
lc_ctrl_tl_intg_err 2.520s 127.969us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 2.520s 127.969us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 6.380s 195.782us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 8.050s 4398.465us 1 1 100.00
lc_ctrl_sec_cm 5.910s 146.560us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 8.050s 4398.465us 1 1 100.00
lc_ctrl_sec_cm 5.910s 146.560us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 8.050s 4398.465us 1 1 100.00
lc_ctrl_sec_cm 5.910s 146.560us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 8.050s 4398.465us 1 1 100.00
lc_ctrl_sec_cm 5.910s 146.560us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 8.050s 4398.465us 1 1 100.00
lc_ctrl_sec_cm 5.910s 146.560us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 8.050s 4398.465us 1 1 100.00
lc_ctrl_sec_cm 5.910s 146.560us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 8.050s 4398.465us 1 1 100.00
lc_ctrl_sec_cm 5.910s 146.560us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 8.050s 4398.465us 1 1 100.00
lc_ctrl_sec_cm 5.910s 146.560us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 4.280s 1100.611us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 3.880s 101.567us 1 1 100.00
lc_ctrl_jtag_state_post_trans 6.420s 328.281us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 6.220s 876.000us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 6.220s 876.000us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 7.470s 8221.362us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 8.600s 529.829us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 8.600s 529.829us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
lc_ctrl_stress_all_with_rand_reset 28.790s 4958.169us 1 1 100.00