Simulation Results: otbn

 
05/08/2026 15:30:30 DVSim: v1.50.0 sha: 023bd59 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 89.42 %
  • code
  • 81.75 %
  • assert
  • 89.49 %
  • func
  • 97.03 %
  • block
  • 97.73 %
  • line
  • 97.93 %
  • branch
  • 81.82 %
  • toggle
  • 81.04 %
  • FSM
  • 66.20 %
Validation stages
V1
100.00%
V2
92.86%
V2S
96.00%
V3
0.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
otbn_smoke 10.000s 39.455us 1 1 100.00
single_binary 1 1 100.00
otbn_single 12.000s 342.242us 1 1 100.00
csr_hw_reset 1 1 100.00
otbn_csr_hw_reset 30.000s 22.845us 1 1 100.00
csr_rw 1 1 100.00
otbn_csr_rw 30.000s 27.437us 1 1 100.00
csr_bit_bash 1 1 100.00
otbn_csr_bit_bash 33.000s 182.747us 1 1 100.00
csr_aliasing 1 1 100.00
otbn_csr_aliasing 31.000s 14.136us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otbn_csr_mem_rw_with_rand_reset 32.000s 147.880us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otbn_csr_rw 30.000s 27.437us 1 1 100.00
otbn_csr_aliasing 31.000s 14.136us 1 1 100.00
mem_walk 1 1 100.00
otbn_mem_walk 97.000s 10585.837us 1 1 100.00
mem_partial_access 1 1 100.00
otbn_mem_partial_access 27.000s 336.035us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_recovery 1 1 100.00
otbn_reset 23.000s 255.218us 1 1 100.00
multi_error 0 1 0.00
otbn_multi_err 52.000s 843.688us 0 1 0.00
back_to_back 1 1 100.00
otbn_multi 68.000s 796.202us 1 1 100.00
stress_all 1 1 100.00
otbn_stress_all 87.000s 3423.342us 1 1 100.00
lc_escalation 1 1 100.00
otbn_escalate 32.000s 185.818us 1 1 100.00
zero_state_err_urnd 1 1 100.00
otbn_zero_state_err_urnd 6.000s 58.355us 1 1 100.00
sw_errs_fatal_chk 1 1 100.00
otbn_sw_errs_fatal_chk 9.000s 64.799us 1 1 100.00
alert_test 1 1 100.00
otbn_alert_test 32.000s 104.535us 1 1 100.00
intr_test 1 1 100.00
otbn_intr_test 3.000s 30.409us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otbn_tl_errors 8.000s 155.553us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otbn_tl_errors 8.000s 155.553us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otbn_csr_hw_reset 30.000s 22.845us 1 1 100.00
otbn_csr_rw 30.000s 27.437us 1 1 100.00
otbn_csr_aliasing 31.000s 14.136us 1 1 100.00
otbn_same_csr_outstanding 4.000s 65.713us 1 1 100.00
tl_d_partial_access 4 4 100.00
otbn_csr_hw_reset 30.000s 22.845us 1 1 100.00
otbn_csr_rw 30.000s 27.437us 1 1 100.00
otbn_csr_aliasing 31.000s 14.136us 1 1 100.00
otbn_same_csr_outstanding 4.000s 65.713us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mem_integrity 2 2 100.00
otbn_imem_err 9.000s 38.476us 1 1 100.00
otbn_dmem_err 33.000s 38.744us 1 1 100.00
internal_integrity 4 4 100.00
otbn_alu_bignum_mod_err 37.000s 21.319us 1 1 100.00
otbn_controller_ispr_rdata_err 39.000s 42.835us 1 1 100.00
otbn_mac_bignum_acc_err 9.000s 375.872us 1 1 100.00
otbn_urnd_err 5.000s 16.762us 1 1 100.00
illegal_bus_access 1 1 100.00
otbn_illegal_mem_acc 25.000s 16.609us 1 1 100.00
otbn_mem_gnt_acc_err 1 1 100.00
otbn_mem_gnt_acc_err 6.000s 25.127us 1 1 100.00
otbn_non_sec_partial_wipe 1 1 100.00
otbn_partial_wipe 11.000s 59.134us 1 1 100.00
tl_intg_err 2 2 100.00
otbn_sec_cm 194.000s 1780.031us 1 1 100.00
otbn_tl_intg_err 13.000s 203.898us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
otbn_passthru_mem_tl_intg_err 27.000s 133.944us 1 1 100.00
prim_fsm_check 1 1 100.00
otbn_sec_cm 194.000s 1780.031us 1 1 100.00
prim_count_check 1 1 100.00
otbn_sec_cm 194.000s 1780.031us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
otbn_smoke 10.000s 39.455us 1 1 100.00
sec_cm_data_mem_integrity 1 1 100.00
otbn_dmem_err 33.000s 38.744us 1 1 100.00
sec_cm_instruction_mem_integrity 1 1 100.00
otbn_imem_err 9.000s 38.476us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otbn_tl_intg_err 13.000s 203.898us 1 1 100.00
sec_cm_controller_fsm_global_esc 1 1 100.00
otbn_escalate 32.000s 185.818us 1 1 100.00
sec_cm_controller_fsm_local_esc 5 5 100.00
otbn_imem_err 9.000s 38.476us 1 1 100.00
otbn_dmem_err 33.000s 38.744us 1 1 100.00
otbn_zero_state_err_urnd 6.000s 58.355us 1 1 100.00
otbn_illegal_mem_acc 25.000s 16.609us 1 1 100.00
otbn_sec_cm 194.000s 1780.031us 1 1 100.00
sec_cm_controller_fsm_sparse 1 1 100.00
otbn_sec_cm 194.000s 1780.031us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
otbn_single 12.000s 342.242us 1 1 100.00
sec_cm_scramble_ctrl_fsm_local_esc 5 5 100.00
otbn_imem_err 9.000s 38.476us 1 1 100.00
otbn_dmem_err 33.000s 38.744us 1 1 100.00
otbn_zero_state_err_urnd 6.000s 58.355us 1 1 100.00
otbn_illegal_mem_acc 25.000s 16.609us 1 1 100.00
otbn_sec_cm 194.000s 1780.031us 1 1 100.00
sec_cm_scramble_ctrl_fsm_sparse 1 1 100.00
otbn_sec_cm 194.000s 1780.031us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_global_esc 1 1 100.00
otbn_escalate 32.000s 185.818us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_local_esc 5 5 100.00
otbn_imem_err 9.000s 38.476us 1 1 100.00
otbn_dmem_err 33.000s 38.744us 1 1 100.00
otbn_zero_state_err_urnd 6.000s 58.355us 1 1 100.00
otbn_illegal_mem_acc 25.000s 16.609us 1 1 100.00
otbn_sec_cm 194.000s 1780.031us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_sparse 1 1 100.00
otbn_sec_cm 194.000s 1780.031us 1 1 100.00
sec_cm_data_reg_sw_sca 1 1 100.00
otbn_single 12.000s 342.242us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
otbn_ctrl_redun 31.000s 27.105us 1 1 100.00
sec_cm_pc_ctrl_flow_redun 1 1 100.00
otbn_pc_ctrl_flow_redun 9.000s 20.619us 1 1 100.00
sec_cm_rnd_bus_consistency 1 1 100.00
otbn_rnd_sec_cm 52.000s 212.611us 1 1 100.00
sec_cm_rnd_rng_digest 1 1 100.00
otbn_rnd_sec_cm 52.000s 212.611us 1 1 100.00
sec_cm_rf_base_data_reg_sw_integrity 1 1 100.00
otbn_rf_base_intg_err 8.000s 70.803us 1 1 100.00
sec_cm_rf_base_data_reg_sw_glitch_detect 1 1 100.00
otbn_sec_cm 194.000s 1780.031us 1 1 100.00
sec_cm_stack_wr_ptr_ctr_redun 1 1 100.00
otbn_sec_cm 194.000s 1780.031us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_integrity 1 1 100.00
otbn_rf_bignum_intg_err 9.000s 52.989us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_glitch_detect 1 1 100.00
otbn_sec_cm 194.000s 1780.031us 1 1 100.00
sec_cm_loop_stack_ctr_redun 1 1 100.00
otbn_sec_cm 194.000s 1780.031us 1 1 100.00
sec_cm_loop_stack_addr_integrity 0 1 0.00
otbn_stack_addr_integ_chk 5.000s 19.474us 0 1 0.00
sec_cm_call_stack_addr_integrity 0 1 0.00
otbn_stack_addr_integ_chk 5.000s 19.474us 0 1 0.00
sec_cm_start_stop_ctrl_state_consistency 1 1 100.00
otbn_sec_wipe_err 5.000s 26.795us 1 1 100.00
sec_cm_data_mem_sec_wipe 1 1 100.00
otbn_single 12.000s 342.242us 1 1 100.00
sec_cm_instruction_mem_sec_wipe 1 1 100.00
otbn_single 12.000s 342.242us 1 1 100.00
sec_cm_data_reg_sw_sec_wipe 1 1 100.00
otbn_single 12.000s 342.242us 1 1 100.00
sec_cm_write_mem_integrity 1 1 100.00
otbn_multi 68.000s 796.202us 1 1 100.00
sec_cm_ctrl_flow_count 1 1 100.00
otbn_single 12.000s 342.242us 1 1 100.00
sec_cm_ctrl_flow_sca 1 1 100.00
otbn_single 12.000s 342.242us 1 1 100.00
sec_cm_data_mem_sw_noaccess 1 1 100.00
otbn_sw_no_acc 5.000s 55.398us 1 1 100.00
sec_cm_key_sideload 1 1 100.00
otbn_single 12.000s 342.242us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
otbn_sec_cm 194.000s 1780.031us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
otbn_stress_all_with_rand_reset 304.000s 1198.237us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
otbn_smoke_vectorized 7.000s 75.063us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (otbn_scoreboard.sv:551) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a recov alert but it still hasn't arrived. 1 test run
otbn_multi_err 16540722539044386233537780645101219526631319828101691194625555950964050930659 375
UVM_INFO @ 843687963 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1287) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
otbn_stress_all_with_rand_reset 21024594738718099539905987629924380484982358921496255279880302725279311497195 311
UVM_INFO @ 1198237079 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed 1 test run
otbn_stack_addr_integ_chk 48198894592452435881129630211806880554451130631688603668702049347514394412884 124
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,158): (time 19474417 PS) Assertion tb.model_if.NoModelErrs has failed
UVM_ERROR @ 19474417 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 19474417 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---