Simulation Results: pwrmgr

 
05/08/2026 15:30:30 DVSim: v1.50.0 sha: 023bd59 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.42 %
  • code
  • 95.70 %
  • assert
  • 98.69 %
  • func
  • 97.86 %
  • line
  • 99.09 %
  • branch
  • 96.37 %
  • cond
  • 95.90 %
  • toggle
  • 91.15 %
  • FSM
  • 96.00 %
Validation stages
V1
100.00%
V2
93.33%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
pwrmgr_smoke 0.680s 40.303us 1 1 100.00
csr_hw_reset 1 1 100.00
pwrmgr_csr_hw_reset 0.710s 27.966us 1 1 100.00
csr_rw 1 1 100.00
pwrmgr_csr_rw 0.600s 60.233us 1 1 100.00
csr_bit_bash 1 1 100.00
pwrmgr_csr_bit_bash 1.600s 214.213us 1 1 100.00
csr_aliasing 1 1 100.00
pwrmgr_csr_aliasing 0.980s 46.280us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
pwrmgr_csr_mem_rw_with_rand_reset 0.930s 71.290us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
pwrmgr_csr_rw 0.600s 60.233us 1 1 100.00
pwrmgr_csr_aliasing 0.980s 46.280us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
wakeup 1 1 100.00
pwrmgr_wakeup 0.850s 120.992us 1 1 100.00
control_clks 1 1 100.00
pwrmgr_wakeup 0.850s 120.992us 1 1 100.00
aborted_low_power 2 2 100.00
pwrmgr_aborted_low_power 0.780s 131.347us 1 1 100.00
pwrmgr_lowpower_invalid 0.810s 86.066us 1 1 100.00
reset 2 2 100.00
pwrmgr_reset 0.830s 107.236us 1 1 100.00
pwrmgr_reset_invalid 0.720s 129.876us 1 1 100.00
main_power_glitch_reset 1 1 100.00
pwrmgr_reset 0.830s 107.236us 1 1 100.00
reset_wakeup_race 1 1 100.00
pwrmgr_wakeup_reset 0.720s 59.516us 1 1 100.00
lowpower_wakeup_race 1 1 100.00
pwrmgr_lowpower_wakeup_race 0.920s 304.832us 1 1 100.00
disable_rom_integrity_check 0 1 0.00
pwrmgr_disable_rom_integrity_check 2.000s 1000.000us 0 1 0.00
stress_all 1 1 100.00
pwrmgr_stress_all 4.540s 2283.824us 1 1 100.00
intr_test 1 1 100.00
pwrmgr_intr_test 0.630s 25.157us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
pwrmgr_tl_errors 1.540s 723.730us 1 1 100.00
tl_d_illegal_access 1 1 100.00
pwrmgr_tl_errors 1.540s 723.730us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
pwrmgr_csr_hw_reset 0.710s 27.966us 1 1 100.00
pwrmgr_csr_rw 0.600s 60.233us 1 1 100.00
pwrmgr_csr_aliasing 0.980s 46.280us 1 1 100.00
pwrmgr_same_csr_outstanding 0.770s 40.317us 1 1 100.00
tl_d_partial_access 4 4 100.00
pwrmgr_csr_hw_reset 0.710s 27.966us 1 1 100.00
pwrmgr_csr_rw 0.600s 60.233us 1 1 100.00
pwrmgr_csr_aliasing 0.980s 46.280us 1 1 100.00
pwrmgr_same_csr_outstanding 0.770s 40.317us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
pwrmgr_tl_intg_err 0.960s 137.417us 1 1 100.00
pwrmgr_sec_cm 1.010s 385.108us 1 1 100.00
prim_count_check 1 1 100.00
pwrmgr_sec_cm 1.010s 385.108us 1 1 100.00
prim_fsm_check 1 1 100.00
pwrmgr_sec_cm 1.010s 385.108us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
pwrmgr_tl_intg_err 0.960s 137.417us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
pwrmgr_sec_cm_lc_ctrl_intersig_mubi 1.470s 829.863us 1 1 100.00
sec_cm_rom_ctrl_intersig_mubi 2 2 100.00
pwrmgr_wakeup_reset 0.720s 59.516us 1 1 100.00
pwrmgr_repeat_wakeup_reset 2.150s 846.080us 1 1 100.00
sec_cm_rstmgr_intersig_mubi 1 1 100.00
pwrmgr_sec_cm_rstmgr_intersig_mubi 0.730s 94.692us 1 1 100.00
sec_cm_esc_rx_clk_bkgn_chk 1 1 100.00
pwrmgr_esc_clk_rst_malfunc 0.590s 36.182us 1 1 100.00
sec_cm_esc_rx_clk_local_esc 1 1 100.00
pwrmgr_sec_cm 1.010s 385.108us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
pwrmgr_sec_cm 1.010s 385.108us 1 1 100.00
sec_cm_fsm_terminal 1 1 100.00
pwrmgr_sec_cm 1.010s 385.108us 1 1 100.00
sec_cm_ctrl_flow_global_esc 1 1 100.00
pwrmgr_global_esc 0.630s 83.820us 1 1 100.00
sec_cm_main_pd_rst_local_esc 1 1 100.00
pwrmgr_glitch 0.670s 68.484us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
pwrmgr_sec_cm_ctrl_config_regwen 0.980s 205.035us 1 1 100.00
sec_cm_wakeup_config_regwen 1 1 100.00
pwrmgr_csr_rw 0.600s 60.233us 1 1 100.00
sec_cm_reset_config_regwen 1 1 100.00
pwrmgr_csr_rw 0.600s 60.233us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
escalation_timeout 1 1 100.00
pwrmgr_escalation_timeout 0.810s 360.842us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
pwrmgr_stress_all_with_rand_reset 2.560s 1699.680us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 1 test run
pwrmgr_disable_rom_integrity_check 103573611078007799287240014242750235372512041450078970560206883871409441223990 85
UVM_INFO @ 1000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---