| V1 |
|
0.00% |
| V2 |
|
0.00% |
| V2S |
|
0.00% |
| V3 |
|
0.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 0 | 1 | 0.00 | |||
| rom_ctrl_smoke | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_hw_reset | 0 | 1 | 0.00 | |||
| rom_ctrl_csr_hw_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_rw | 0 | 1 | 0.00 | |||
| rom_ctrl_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_bit_bash | 0 | 1 | 0.00 | |||
| rom_ctrl_csr_bit_bash | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_aliasing | 0 | 1 | 0.00 | |||
| rom_ctrl_csr_aliasing | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_mem_rw_with_rand_reset | 0 | 1 | 0.00 | |||
| rom_ctrl_csr_mem_rw_with_rand_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| regwen_csr_and_corresponding_lockable_csr | 0 | 2 | 0.00 | |||
| rom_ctrl_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_ctrl_csr_aliasing | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| mem_walk | 0 | 1 | 0.00 | |||
| rom_ctrl_mem_walk | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| mem_partial_access | 0 | 1 | 0.00 | |||
| rom_ctrl_mem_partial_access | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| max_throughput_chk | 0 | 1 | 0.00 | |||
| rom_ctrl_max_throughput_chk | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| stress_all | 0 | 1 | 0.00 | |||
| rom_ctrl_stress_all | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| kmac_err_chk | 0 | 1 | 0.00 | |||
| rom_ctrl_kmac_err_chk | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| alert_test | 0 | 1 | 0.00 | |||
| rom_ctrl_alert_test | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_oob_addr_access | 0 | 1 | 0.00 | |||
| rom_ctrl_tl_errors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_illegal_access | 0 | 1 | 0.00 | |||
| rom_ctrl_tl_errors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_outstanding_access | 0 | 4 | 0.00 | |||
| rom_ctrl_csr_hw_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_ctrl_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_ctrl_csr_aliasing | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_ctrl_same_csr_outstanding | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_partial_access | 0 | 4 | 0.00 | |||
| rom_ctrl_csr_hw_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_ctrl_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_ctrl_csr_aliasing | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_ctrl_same_csr_outstanding | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| corrupt_sig_fatal_chk | 0 | 1 | 0.00 | |||
| rom_ctrl_corrupt_sig_fatal_chk | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| passthru_mem_tl_intg_err | 0 | 1 | 0.00 | |||
| rom_ctrl_passthru_mem_tl_intg_err | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_intg_err | 0 | 2 | 0.00 | |||
| rom_ctrl_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_ctrl_tl_intg_err | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| prim_fsm_check | 0 | 1 | 0.00 | |||
| rom_ctrl_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| prim_count_check | 0 | 1 | 0.00 | |||
| rom_ctrl_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_checker_ctr_consistency | 0 | 1 | 0.00 | |||
| rom_ctrl_corrupt_sig_fatal_chk | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_checker_ctrl_flow_consistency | 0 | 1 | 0.00 | |||
| rom_ctrl_corrupt_sig_fatal_chk | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_checker_fsm_local_esc | 0 | 1 | 0.00 | |||
| rom_ctrl_corrupt_sig_fatal_chk | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_compare_ctrl_flow_consistency | 0 | 1 | 0.00 | |||
| rom_ctrl_corrupt_sig_fatal_chk | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_compare_ctr_consistency | 0 | 1 | 0.00 | |||
| rom_ctrl_corrupt_sig_fatal_chk | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_compare_ctr_redun | 0 | 1 | 0.00 | |||
| rom_ctrl_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_fsm_sparse | 0 | 1 | 0.00 | |||
| rom_ctrl_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_mem_scramble | 0 | 1 | 0.00 | |||
| rom_ctrl_smoke | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_mem_digest | 0 | 1 | 0.00 | |||
| rom_ctrl_smoke | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_intersig_mubi | 0 | 1 | 0.00 | |||
| rom_ctrl_smoke | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_bus_integrity | 0 | 1 | 0.00 | |||
| rom_ctrl_tl_intg_err | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_bus_local_esc | 0 | 2 | 0.00 | |||
| rom_ctrl_corrupt_sig_fatal_chk | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_ctrl_kmac_err_chk | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_mux_mubi | 0 | 1 | 0.00 | |||
| rom_ctrl_corrupt_sig_fatal_chk | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_mux_consistency | 0 | 1 | 0.00 | |||
| rom_ctrl_corrupt_sig_fatal_chk | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_ctrl_redun | 0 | 1 | 0.00 | |||
| rom_ctrl_corrupt_sig_fatal_chk | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_ctrl_mem_integrity | 0 | 1 | 0.00 | |||
| rom_ctrl_passthru_mem_tl_intg_err | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_tlul_fifo_ctr_redun | 0 | 1 | 0.00 | |||
| rom_ctrl_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| stress_all_with_rand_reset | 0 | 1 | 0.00 | |||
| rom_ctrl_stress_all_with_rand_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| Job cancelled because one of its dependencies failed or was killed. | 20 test runs | |||
| rom_ctrl_smoke | 76960883360628112944967076418641350298655188382165407251584107319107943724147 | None | ||
| rom_ctrl_stress_all | 102390377766504309938740539245239551270091187825879158391469253669048589552208 | None | ||
| rom_ctrl_max_throughput_chk | 67930353842304439531372013992708235985538186789406706945252836449728617857336 | None | ||
| rom_ctrl_corrupt_sig_fatal_chk | 8091483445079697064146882449188545527471061132513795636370304840326649455000 | None | ||
| rom_ctrl_kmac_err_chk | 25110518933294154515914775020692917695690819525213154110354248916295964072477 | None | ||
| rom_ctrl_stress_all_with_rand_reset | 110877841980509948617475150976027389810646034782803540862324501256251561311297 | None | ||
| rom_ctrl_sec_cm | 39133783917101740942900710566558600050585163194979020853081970893545548838690 | None | ||
| rom_ctrl_passthru_mem_tl_intg_err | 91682327991789385774614772534477088811752343289540154991387661274053612993747 | None | ||
| rom_ctrl_tl_errors | 86661708494740111398100957813372425649917839897912374842073753814713141321105 | None | ||
| rom_ctrl_tl_intg_err | 79535053975643279618624380094785301391696286677036985721436636796821876564642 | None | ||
| rom_ctrl_alert_test | 17183159319977409687694414815694233294595329247182267542679326030587757207555 | None | ||
| rom_ctrl_mem_walk | 108733907855423894142004932832509319967619931581320372304423885971399911995308 | None | ||
| rom_ctrl_mem_partial_access | 3659216716477349944641846811540039721006390014114412203795200346044101121259 | None | ||
| rom_ctrl_csr_hw_reset | 10727974385619224214502950407040571481967736915499839384182514753035478651169 | None | ||
| rom_ctrl_csr_rw | 100640754293395875861530659797269493712708076846651599526025616474120068657263 | None | ||
| rom_ctrl_csr_bit_bash | 67010763114820005503836709097784092604510325565539216661412626787523603038126 | None | ||
| rom_ctrl_csr_aliasing | 85000915401484349447529126436130319269849242320332780279787463546430710180570 | None | ||
| rom_ctrl_same_csr_outstanding | 63122231556294502081921390836483082339270409947329107416531442191891911146791 | None | ||
| rom_ctrl_csr_mem_rw_with_rand_reset | 61397845828961033366565638155628866931668821340046359664093497323198175583729 | None | ||
| rom_ctrl | None | None | ||
| Job returned a non-zero exit code: * | 2 test runs | |||
| default | None | None |
/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-vcs/default/fusesoc-work/183032: No such file or directory.
/tmp/vcs_20260805153157_128870/.stack_annotator_gdb_cmd_file_vtFgwZ:2: Error in sourced command file:
No stack.
Process VmPeak: 437100 kb, VmSize: 421496 kb
System Free Memory: 184581408 kb, System Free Swap: 0 kb
Completed context dump phase location* 'Module' 'Module'
CPU time: 11.474 seconds to compile
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:36: do_build] Error 255
|
|
| cover_reg_top | None | None |
/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-vcs/cover_reg_top/fusesoc-work/105114: No such file or directory.
/tmp/vcs_20260805153054_11182/.stack_annotator_gdb_cmd_file_3RXqKF:2: Error in sourced command file:
No stack.
Process VmPeak: 438004 kb, VmSize: 422400 kb
System Free Memory: 183590720 kb, System Free Swap: 0 kb
Completed context dump phase location* 'Module' 'Module'
CPU time: 13.009 seconds to compile
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:36: do_build] Error 255
|
|
| Job cancelled because all of its dependencies failed or were killed. | 1 test run | |||
| rom_ctrl | None | None | ||