Simulation Results: rstmgr

 
05/08/2026 15:30:30 DVSim: v1.50.0 sha: 023bd59 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.22 %
  • code
  • 99.36 %
  • assert
  • 98.53 %
  • func
  • 96.77 %
  • line
  • 99.51 %
  • branch
  • 99.83 %
  • cond
  • 98.75 %
  • toggle
  • 99.33 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rstmgr_smoke 1.410s 279.873us 1 1 100.00
csr_hw_reset 1 1 100.00
rstmgr_csr_hw_reset 0.780s 101.447us 1 1 100.00
csr_rw 1 1 100.00
rstmgr_csr_rw 0.970s 91.448us 1 1 100.00
csr_bit_bash 1 1 100.00
rstmgr_csr_bit_bash 9.440s 2830.715us 1 1 100.00
csr_aliasing 1 1 100.00
rstmgr_csr_aliasing 1.690s 158.689us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rstmgr_csr_mem_rw_with_rand_reset 1.210s 110.660us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rstmgr_csr_rw 0.970s 91.448us 1 1 100.00
rstmgr_csr_aliasing 1.690s 158.689us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_stretcher 1 1 100.00
rstmgr_por_stretcher 1.090s 162.787us 1 1 100.00
sw_rst 1 1 100.00
rstmgr_sw_rst 1.790s 191.110us 1 1 100.00
sw_rst_reset_race 1 1 100.00
rstmgr_sw_rst_reset_race 0.830s 119.774us 1 1 100.00
reset_info 1 1 100.00
rstmgr_reset 4.630s 1887.667us 1 1 100.00
cpu_info 1 1 100.00
rstmgr_reset 4.630s 1887.667us 1 1 100.00
alert_info 1 1 100.00
rstmgr_reset 4.630s 1887.667us 1 1 100.00
reset_info_capture 1 1 100.00
rstmgr_reset 4.630s 1887.667us 1 1 100.00
stress_all 1 1 100.00
rstmgr_stress_all 17.690s 7691.838us 1 1 100.00
alert_test 1 1 100.00
rstmgr_alert_test 0.730s 67.244us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rstmgr_tl_errors 2.760s 490.412us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rstmgr_tl_errors 2.760s 490.412us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rstmgr_csr_hw_reset 0.780s 101.447us 1 1 100.00
rstmgr_csr_rw 0.970s 91.448us 1 1 100.00
rstmgr_csr_aliasing 1.690s 158.689us 1 1 100.00
rstmgr_same_csr_outstanding 0.990s 154.619us 1 1 100.00
tl_d_partial_access 4 4 100.00
rstmgr_csr_hw_reset 0.780s 101.447us 1 1 100.00
rstmgr_csr_rw 0.970s 91.448us 1 1 100.00
rstmgr_csr_aliasing 1.690s 158.689us 1 1 100.00
rstmgr_same_csr_outstanding 0.990s 154.619us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rstmgr_sec_cm 18.750s 17301.791us 1 1 100.00
rstmgr_tl_intg_err 1.520s 432.570us 1 1 100.00
prim_count_check 1 1 100.00
rstmgr_sec_cm 18.750s 17301.791us 1 1 100.00
prim_fsm_check 1 1 100.00
rstmgr_sec_cm 18.750s 17301.791us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rstmgr_tl_intg_err 1.520s 432.570us 1 1 100.00
sec_cm_scan_intersig_mubi 1 1 100.00
rstmgr_sec_cm_scan_intersig_mubi 0.920s 115.163us 1 1 100.00
sec_cm_leaf_rst_bkgn_chk 1 1 100.00
rstmgr_leaf_rst_cnsty 6.920s 2803.646us 1 1 100.00
sec_cm_leaf_rst_shadow 1 1 100.00
rstmgr_leaf_rst_shadow_attack 1.070s 302.537us 1 1 100.00
sec_cm_leaf_fsm_sparse 1 1 100.00
rstmgr_sec_cm 18.750s 17301.791us 1 1 100.00
sec_cm_sw_rst_config_regwen 1 1 100.00
rstmgr_csr_rw 0.970s 91.448us 1 1 100.00
sec_cm_dump_ctrl_config_regwen 1 1 100.00
rstmgr_csr_rw 0.970s 91.448us 1 1 100.00