Simulation Results: rv_timer

 
05/08/2026 15:30:30 DVSim: v1.50.0 sha: 023bd59 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.31 %
  • code
  • 94.66 %
  • assert
  • 98.09 %
  • func
  • 96.18 %
  • line
  • 100.00 %
  • branch
  • 100.00 %
  • cond
  • 100.00 %
  • toggle
  • 78.66 %
Validation stages
V1
100.00%
V2
90.91%
V2S
100.00%
V3
33.33%
Testpoint Test Max Runtime Sim Time Pass Total %
random 1 1 100.00
rv_timer_random 1.160s 1724.854us 1 1 100.00
csr_hw_reset 1 1 100.00
rv_timer_csr_hw_reset 0.650s 29.279us 1 1 100.00
csr_rw 1 1 100.00
rv_timer_csr_rw 0.600s 43.741us 1 1 100.00
csr_bit_bash 1 1 100.00
rv_timer_csr_bit_bash 2.190s 692.536us 1 1 100.00
csr_aliasing 1 1 100.00
rv_timer_csr_aliasing 0.810s 38.310us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rv_timer_csr_mem_rw_with_rand_reset 0.920s 206.403us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rv_timer_csr_rw 0.600s 43.741us 1 1 100.00
rv_timer_csr_aliasing 0.810s 38.310us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
random_reset 0 1 0.00
rv_timer_random_reset 0.710s 74.117us 0 1 0.00
disabled 1 1 100.00
rv_timer_disabled 1.470s 979.471us 1 1 100.00
cfg_update_on_fly 1 1 100.00
rv_timer_cfg_update_on_fly 516.310s 599567.278us 1 1 100.00
no_interrupt_test 1 1 100.00
rv_timer_cfg_update_on_fly 516.310s 599567.278us 1 1 100.00
stress 1 1 100.00
rv_timer_stress_all 1.610s 6775.280us 1 1 100.00
alert_test 1 1 100.00
rv_timer_alert_test 0.560s 30.142us 1 1 100.00
intr_test 1 1 100.00
rv_timer_intr_test 0.560s 13.026us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rv_timer_tl_errors 1.040s 124.433us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rv_timer_tl_errors 1.040s 124.433us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rv_timer_csr_hw_reset 0.650s 29.279us 1 1 100.00
rv_timer_csr_rw 0.600s 43.741us 1 1 100.00
rv_timer_csr_aliasing 0.810s 38.310us 1 1 100.00
rv_timer_same_csr_outstanding 0.650s 67.138us 1 1 100.00
tl_d_partial_access 4 4 100.00
rv_timer_csr_hw_reset 0.650s 29.279us 1 1 100.00
rv_timer_csr_rw 0.600s 43.741us 1 1 100.00
rv_timer_csr_aliasing 0.810s 38.310us 1 1 100.00
rv_timer_same_csr_outstanding 0.650s 67.138us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rv_timer_sec_cm 0.810s 100.405us 1 1 100.00
rv_timer_tl_intg_err 0.820s 51.175us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rv_timer_tl_intg_err 0.820s 51.175us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
min_value 0 1 0.00
rv_timer_min 0.700s 355.280us 0 1 0.00
max_value 0 1 0.00
rv_timer_max 0.690s 483.457us 0 1 0.00
stress_all_with_rand_reset 1 1 100.00
rv_timer_stress_all_with_rand_reset 15.200s 9614.274us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * 2 test runs
rv_timer_min 69893819079096195099060636327161133202801324129152531640108082090725697693864 77
UVM_INFO @ 355279705 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 6590955293787278635908994155773522426546380470544344350466201920196660496881 75
UVM_INFO @ 74116772 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_timer_scoreboard.sv:231) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) 1 test run
rv_timer_max 66226180633682687805049698678752814343886876386434554609231524604780887964973 76
UVM_INFO @ 483456941 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---