Simulation Results: spi_host

 
05/08/2026 15:30:30 DVSim: v1.50.0 sha: 023bd59 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 92.14 %
  • code
  • 91.16 %
  • assert
  • 96.60 %
  • func
  • 88.66 %
  • block
  • 96.78 %
  • line
  • 98.54 %
  • branch
  • 93.05 %
  • toggle
  • 73.07 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
95.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_host_smoke 11.000s 1264.813us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_host_csr_hw_reset 1.000s 19.050us 1 1 100.00
csr_rw 1 1 100.00
spi_host_csr_rw 2.000s 18.791us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_host_csr_bit_bash 3.000s 50.102us 1 1 100.00
csr_aliasing 1 1 100.00
spi_host_csr_aliasing 1.000s 23.621us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_host_csr_mem_rw_with_rand_reset 2.000s 61.309us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_host_csr_rw 2.000s 18.791us 1 1 100.00
spi_host_csr_aliasing 1.000s 23.621us 1 1 100.00
mem_walk 1 1 100.00
spi_host_mem_walk 1.000s 17.775us 1 1 100.00
mem_partial_access 1 1 100.00
spi_host_mem_partial_access 1.000s 62.304us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
performance 1 1 100.00
spi_host_performance 1.000s 26.790us 1 1 100.00
error_event_intr 3 3 100.00
spi_host_overflow_underflow 2.000s 57.228us 1 1 100.00
spi_host_error_cmd 1.000s 53.774us 1 1 100.00
spi_host_event 10.000s 6859.383us 1 1 100.00
clock_rate 1 1 100.00
spi_host_speed 2.000s 44.209us 1 1 100.00
speed 1 1 100.00
spi_host_speed 2.000s 44.209us 1 1 100.00
chip_select_timing 1 1 100.00
spi_host_speed 2.000s 44.209us 1 1 100.00
upper_range_clkdiv 0 1 0.00
spi_host_upper_range_clkdiv 141.000s 200000.000us 0 1 0.00
sw_reset 1 1 100.00
spi_host_sw_reset 17.000s 1743.545us 1 1 100.00
passthrough_mode 1 1 100.00
spi_host_passthrough_mode 1.000s 29.782us 1 1 100.00
cpol_cpha 1 1 100.00
spi_host_speed 2.000s 44.209us 1 1 100.00
full_cycle 1 1 100.00
spi_host_speed 2.000s 44.209us 1 1 100.00
duplex 1 1 100.00
spi_host_smoke 11.000s 1264.813us 1 1 100.00
tx_rx_only 1 1 100.00
spi_host_smoke 11.000s 1264.813us 1 1 100.00
stress_all 1 1 100.00
spi_host_stress_all 55.000s 2598.274us 1 1 100.00
spien 1 1 100.00
spi_host_spien 88.000s 4558.535us 1 1 100.00
stall 1 1 100.00
spi_host_status_stall 83.000s 93723.890us 1 1 100.00
Idlecsbactive 1 1 100.00
spi_host_idlecsbactive 2.000s 83.678us 1 1 100.00
data_fifo_status 1 1 100.00
spi_host_overflow_underflow 2.000s 57.228us 1 1 100.00
alert_test 1 1 100.00
spi_host_alert_test 1.000s 40.114us 1 1 100.00
intr_test 1 1 100.00
spi_host_intr_test 1.000s 221.854us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_host_tl_errors 2.000s 310.508us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_host_tl_errors 2.000s 310.508us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_host_csr_hw_reset 1.000s 19.050us 1 1 100.00
spi_host_csr_rw 2.000s 18.791us 1 1 100.00
spi_host_csr_aliasing 1.000s 23.621us 1 1 100.00
spi_host_same_csr_outstanding 1.000s 28.399us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_host_csr_hw_reset 1.000s 19.050us 1 1 100.00
spi_host_csr_rw 2.000s 18.791us 1 1 100.00
spi_host_csr_aliasing 1.000s 23.621us 1 1 100.00
spi_host_same_csr_outstanding 1.000s 28.399us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_host_tl_intg_err 2.000s 273.106us 1 1 100.00
spi_host_sec_cm 2.000s 46.298us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_host_tl_intg_err 2.000s 273.106us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 1 test run
spi_host_upper_range_clkdiv 32664811383516609376979387811868557633341780377770573865068804454472712882415 115
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---