Simulation Results: sysrst_ctrl

 
05/08/2026 15:30:30 DVSim: v1.50.0 sha: 023bd59 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 82.24 %
  • code
  • 90.56 %
  • assert
  • 89.37 %
  • func
  • 66.80 %
  • line
  • 95.89 %
  • branch
  • 96.40 %
  • cond
  • 92.91 %
  • toggle
  • 99.66 %
  • FSM
  • 67.95 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sysrst_ctrl_smoke 1.520s 2130.345us 1 1 100.00
input_output_inverted 1 1 100.00
sysrst_ctrl_in_out_inverted 2.260s 2502.785us 1 1 100.00
combo_detect_ec_rst 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst 3.540s 2188.814us 1 1 100.00
combo_detect_ec_rst_with_pre_cond 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst_with_pre_cond 1.720s 2552.076us 1 1 100.00
csr_hw_reset 1 1 100.00
sysrst_ctrl_csr_hw_reset 3.290s 6100.865us 1 1 100.00
csr_rw 1 1 100.00
sysrst_ctrl_csr_rw 3.860s 2052.012us 1 1 100.00
csr_bit_bash 1 1 100.00
sysrst_ctrl_csr_bit_bash 38.480s 76282.443us 1 1 100.00
csr_aliasing 1 1 100.00
sysrst_ctrl_csr_aliasing 2.980s 2656.903us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sysrst_ctrl_csr_mem_rw_with_rand_reset 1.830s 2066.891us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sysrst_ctrl_csr_rw 3.860s 2052.012us 1 1 100.00
sysrst_ctrl_csr_aliasing 2.980s 2656.903us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
combo_detect 1 1 100.00
sysrst_ctrl_combo_detect 75.850s 94227.077us 1 1 100.00
combo_detect_with_pre_cond 1 1 100.00
sysrst_ctrl_combo_detect_with_pre_cond 66.190s 43011.985us 1 1 100.00
auto_block_key_outputs 1 1 100.00
sysrst_ctrl_auto_blk_key_output 5.640s 3012.835us 1 1 100.00
keyboard_input_triggered_interrupt 1 1 100.00
sysrst_ctrl_edge_detect 2.660s 2322.930us 1 1 100.00
pin_output_keyboard_inversion_control 1 1 100.00
sysrst_ctrl_pin_override_test 2.110s 2519.201us 1 1 100.00
pin_input_value_accessibility 1 1 100.00
sysrst_ctrl_pin_access_test 1.540s 2267.302us 1 1 100.00
ec_power_on_reset 1 1 100.00
sysrst_ctrl_ec_pwr_on_rst 1.820s 2793.410us 1 1 100.00
flash_write_protect_output 1 1 100.00
sysrst_ctrl_flash_wr_prot_out 2.100s 2633.614us 1 1 100.00
ultra_low_power_test 1 1 100.00
sysrst_ctrl_ultra_low_pwr 2.180s 4992.148us 1 1 100.00
sysrst_ctrl_feature_disable 1 1 100.00
sysrst_ctrl_feature_disable 57.310s 37706.612us 1 1 100.00
stress_all 1 1 100.00
sysrst_ctrl_stress_all 12.190s 8388.217us 1 1 100.00
alert_test 1 1 100.00
sysrst_ctrl_alert_test 1.600s 2036.994us 1 1 100.00
intr_test 1 1 100.00
sysrst_ctrl_intr_test 2.390s 2019.023us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sysrst_ctrl_tl_errors 4.150s 2084.025us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sysrst_ctrl_tl_errors 4.150s 2084.025us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sysrst_ctrl_csr_hw_reset 3.290s 6100.865us 1 1 100.00
sysrst_ctrl_csr_rw 3.860s 2052.012us 1 1 100.00
sysrst_ctrl_csr_aliasing 2.980s 2656.903us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 13.760s 8015.971us 1 1 100.00
tl_d_partial_access 4 4 100.00
sysrst_ctrl_csr_hw_reset 3.290s 6100.865us 1 1 100.00
sysrst_ctrl_csr_rw 3.860s 2052.012us 1 1 100.00
sysrst_ctrl_csr_aliasing 2.980s 2656.903us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 13.760s 8015.971us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
sysrst_ctrl_sec_cm 36.090s 42052.957us 1 1 100.00
sysrst_ctrl_tl_intg_err 9.380s 22283.063us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sysrst_ctrl_tl_intg_err 9.380s 22283.063us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sysrst_ctrl_stress_all_with_rand_reset 11.420s 5833.383us 1 1 100.00