Simulation Results: uart

 
05/08/2026 15:30:30 DVSim: v1.50.0 sha: 023bd59 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 83.25 %
  • code
  • 91.65 %
  • assert
  • 98.56 %
  • func
  • 59.55 %
  • line
  • 99.17 %
  • branch
  • 97.44 %
  • cond
  • 95.33 %
  • toggle
  • 74.67 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
uart_smoke 14.550s 5436.691us 1 1 100.00
csr_hw_reset 1 1 100.00
uart_csr_hw_reset 0.900s 83.272us 1 1 100.00
csr_rw 1 1 100.00
uart_csr_rw 0.630s 15.911us 1 1 100.00
csr_bit_bash 1 1 100.00
uart_csr_bit_bash 1.320s 319.782us 1 1 100.00
csr_aliasing 1 1 100.00
uart_csr_aliasing 0.980s 28.093us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
uart_csr_mem_rw_with_rand_reset 1.010s 21.552us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
uart_csr_rw 0.630s 15.911us 1 1 100.00
uart_csr_aliasing 0.980s 28.093us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
base_random_seq 1 1 100.00
uart_tx_rx 3.520s 4859.559us 1 1 100.00
parity 2 2 100.00
uart_smoke 14.550s 5436.691us 1 1 100.00
uart_tx_rx 3.520s 4859.559us 1 1 100.00
parity_error 2 2 100.00
uart_intr 4.860s 13197.540us 1 1 100.00
uart_rx_parity_err 45.430s 161041.837us 1 1 100.00
watermark 2 2 100.00
uart_tx_rx 3.520s 4859.559us 1 1 100.00
uart_intr 4.860s 13197.540us 1 1 100.00
fifo_full 1 1 100.00
uart_fifo_full 139.390s 110236.014us 1 1 100.00
fifo_overflow 1 1 100.00
uart_fifo_overflow 183.520s 195239.552us 1 1 100.00
fifo_reset 1 1 100.00
uart_fifo_reset 80.430s 116431.033us 1 1 100.00
rx_frame_err 1 1 100.00
uart_intr 4.860s 13197.540us 1 1 100.00
rx_break_err 1 1 100.00
uart_intr 4.860s 13197.540us 1 1 100.00
rx_timeout 1 1 100.00
uart_intr 4.860s 13197.540us 1 1 100.00
perf 1 1 100.00
uart_perf 410.730s 17938.597us 1 1 100.00
sys_loopback 1 1 100.00
uart_loopback 1.740s 2738.929us 1 1 100.00
line_loopback 1 1 100.00
uart_loopback 1.740s 2738.929us 1 1 100.00
rx_noise_filter 1 1 100.00
uart_noise_filter 5.050s 5943.719us 1 1 100.00
rx_start_bit_filter 1 1 100.00
uart_rx_start_bit_filter 2.190s 7097.734us 1 1 100.00
tx_overide 1 1 100.00
uart_tx_ovrd 2.020s 3164.855us 1 1 100.00
rx_oversample 1 1 100.00
uart_rx_oversample 5.920s 2847.303us 1 1 100.00
long_b2b_transfer 1 1 100.00
uart_long_xfer_wo_dly 132.500s 78090.911us 1 1 100.00
stress_all 1 1 100.00
uart_stress_all 360.350s 284490.224us 1 1 100.00
alert_test 1 1 100.00
uart_alert_test 0.740s 160.223us 1 1 100.00
intr_test 1 1 100.00
uart_intr_test 0.660s 19.288us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
uart_tl_errors 2.090s 1584.666us 1 1 100.00
tl_d_illegal_access 1 1 100.00
uart_tl_errors 2.090s 1584.666us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
uart_csr_hw_reset 0.900s 83.272us 1 1 100.00
uart_csr_rw 0.630s 15.911us 1 1 100.00
uart_csr_aliasing 0.980s 28.093us 1 1 100.00
uart_same_csr_outstanding 0.940s 36.005us 1 1 100.00
tl_d_partial_access 4 4 100.00
uart_csr_hw_reset 0.900s 83.272us 1 1 100.00
uart_csr_rw 0.630s 15.911us 1 1 100.00
uart_csr_aliasing 0.980s 28.093us 1 1 100.00
uart_same_csr_outstanding 0.940s 36.005us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
uart_sec_cm 0.960s 69.380us 1 1 100.00
uart_tl_intg_err 1.150s 483.786us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
uart_tl_intg_err 1.150s 483.786us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
uart_stress_all_with_rand_reset 25.030s 10318.791us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (uart_scoreboard.sv:501) scoreboard [scoreboard] rxlvl mismatch exp: * (+/-1), act: *, clk_pulses: * 1 test run
uart_stress_all_with_rand_reset 102668779738577529352232073893392449791670980650329889024282039522889761747276 106
UVM_ERROR @ 1805688665 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 1805727127 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 255 [0xff]) reg name: uart_reg_block.rdata
UVM_ERROR @ 1805804051 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 1805842513 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 243 [0xf3]) reg name: uart_reg_block.rdata