Simulation Results: adc_ctrl

 
06/08/2026 15:30:30 DVSim: v1.50.0 sha: 377160a json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 65.84 %
  • code
  • 92.69 %
  • assert
  • 91.73 %
  • func
  • 13.09 %
  • line
  • 98.13 %
  • branch
  • 96.41 %
  • cond
  • 86.06 %
  • toggle
  • 99.05 %
  • FSM
  • 83.78 %
Validation stages
V1
100.00%
V2
52.63%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
adc_ctrl_smoke 2.350s 5789.676us 1 1 100.00
csr_hw_reset 1 1 100.00
adc_ctrl_csr_hw_reset 1.620s 752.127us 1 1 100.00
csr_rw 1 1 100.00
adc_ctrl_csr_rw 0.810s 391.117us 1 1 100.00
csr_bit_bash 1 1 100.00
adc_ctrl_csr_bit_bash 10.600s 26737.130us 1 1 100.00
csr_aliasing 1 1 100.00
adc_ctrl_csr_aliasing 1.340s 816.989us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
adc_ctrl_csr_mem_rw_with_rand_reset 1.680s 572.081us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
adc_ctrl_csr_rw 0.810s 391.117us 1 1 100.00
adc_ctrl_csr_aliasing 1.340s 816.989us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
filters_polled 0 1 0.00
adc_ctrl_filters_polled 1.100s 345.558us 0 1 0.00
filters_polled_fixed 0 1 0.00
adc_ctrl_filters_polled_fixed 0.680s 500.312us 0 1 0.00
filters_interrupt 0 1 0.00
adc_ctrl_filters_interrupt 1.250s 494.303us 0 1 0.00
filters_interrupt_fixed 0 1 0.00
adc_ctrl_filters_interrupt_fixed 0.950s 518.718us 0 1 0.00
filters_wakeup 0 1 0.00
adc_ctrl_filters_wakeup 0.920s 413.601us 0 1 0.00
filters_wakeup_fixed 0 1 0.00
adc_ctrl_filters_wakeup_fixed 0.680s 443.773us 0 1 0.00
filters_both 0 1 0.00
adc_ctrl_filters_both 0.770s 406.835us 0 1 0.00
clock_gating 0 1 0.00
adc_ctrl_clock_gating 0.930s 504.598us 0 1 0.00
poweron_counter 1 1 100.00
adc_ctrl_poweron_counter 2.050s 3930.825us 1 1 100.00
lowpower_counter 1 1 100.00
adc_ctrl_lowpower_counter 32.120s 23703.791us 1 1 100.00
fsm_reset 1 1 100.00
adc_ctrl_fsm_reset 44.910s 131499.593us 1 1 100.00
stress_all 0 1 0.00
adc_ctrl_stress_all 0.910s 865.648us 0 1 0.00
alert_test 1 1 100.00
adc_ctrl_alert_test 1.120s 391.428us 1 1 100.00
intr_test 1 1 100.00
adc_ctrl_intr_test 0.810s 433.105us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
adc_ctrl_tl_errors 2.010s 833.464us 1 1 100.00
tl_d_illegal_access 1 1 100.00
adc_ctrl_tl_errors 2.010s 833.464us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
adc_ctrl_csr_hw_reset 1.620s 752.127us 1 1 100.00
adc_ctrl_csr_rw 0.810s 391.117us 1 1 100.00
adc_ctrl_csr_aliasing 1.340s 816.989us 1 1 100.00
adc_ctrl_same_csr_outstanding 1.030s 2677.081us 1 1 100.00
tl_d_partial_access 4 4 100.00
adc_ctrl_csr_hw_reset 1.620s 752.127us 1 1 100.00
adc_ctrl_csr_rw 0.810s 391.117us 1 1 100.00
adc_ctrl_csr_aliasing 1.340s 816.989us 1 1 100.00
adc_ctrl_same_csr_outstanding 1.030s 2677.081us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
adc_ctrl_sec_cm 7.040s 4621.685us 1 1 100.00
adc_ctrl_tl_intg_err 6.660s 4154.764us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
adc_ctrl_tl_intg_err 6.660s 4154.764us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
adc_ctrl_stress_all_with_rand_reset 9.330s 3782.931us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (adc_ctrl_filter_cfg.sv:57) [adc_ctrl_filter_cfg::make] Backwards min_v/max_v range of [*, *] 10 test runs
adc_ctrl_filters_polled 52679561077451615366247437351307121290902930075721371536104586318626721315759 386
UVM_INFO @ 345558486 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_polled_fixed 158808566035478848128469095686287491275872507973485102371707144352918357546 386
UVM_INFO @ 500312331 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_interrupt 42610850739763484192911159328996707969521467414725821742418885371621461394840 386
UVM_INFO @ 494302699 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_interrupt_fixed 12887530228595205087830232868457410558460036398050755046838970245579280987212 386
UVM_INFO @ 518717537 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_wakeup 98558567245233459103429105070097041047399670029829005292200224443237374326395 386
UVM_INFO @ 413601282 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_wakeup_fixed 32911663354410105985377835990319981662502408408655124142259117619296159267782 386
UVM_INFO @ 443772738 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 88735551404714182372148266781163262651526548671006181998895468163866504258644 386
UVM_INFO @ 504598231 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_both 109334293194124085129430612562212354985766580069104948909821860569039273761974 386
UVM_INFO @ 406834923 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_stress_all_with_rand_reset 66473657989995929385772594883262620901567770975849212868866043506423441699137 446
UVM_INFO @ 3782930626 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_stress_all 114613727371691832982347410393231566456706128924974164559231269531867608215439 387
UVM_INFO @ 865647989 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---