Simulation Results: aes/masked

 
06/08/2026 15:30:30 DVSim: v1.50.0 sha: 377160a json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 87.94 %
  • code
  • 94.27 %
  • assert
  • 98.23 %
  • func
  • 71.32 %
  • block
  • 94.40 %
  • line
  • 96.01 %
  • branch
  • 87.52 %
  • toggle
  • 97.99 %
  • FSM
  • 95.56 %
Validation stages
V1
100.00%
V2
100.00%
V2S
93.75%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 2.000s 84.720us 1 1 100.00
smoke 1 1 100.00
aes_smoke 3.000s 119.520us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 2.000s 59.049us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 2.000s 58.449us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 8.000s 2437.278us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 3.000s 91.791us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 2.000s 100.436us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 2.000s 58.449us 1 1 100.00
aes_csr_aliasing 3.000s 91.791us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 3.000s 119.520us 1 1 100.00
aes_config_error 2.000s 90.816us 1 1 100.00
aes_stress 3.000s 110.964us 1 1 100.00
key_length 3 3 100.00
aes_smoke 3.000s 119.520us 1 1 100.00
aes_config_error 2.000s 90.816us 1 1 100.00
aes_stress 3.000s 110.964us 1 1 100.00
back2back 2 2 100.00
aes_stress 3.000s 110.964us 1 1 100.00
aes_b2b 13.000s 291.139us 1 1 100.00
backpressure 1 1 100.00
aes_stress 3.000s 110.964us 1 1 100.00
multi_message 4 4 100.00
aes_smoke 3.000s 119.520us 1 1 100.00
aes_config_error 2.000s 90.816us 1 1 100.00
aes_stress 3.000s 110.964us 1 1 100.00
aes_alert_reset 2.000s 114.871us 1 1 100.00
failure_test 3 3 100.00
aes_man_cfg_err 3.000s 113.179us 1 1 100.00
aes_config_error 2.000s 90.816us 1 1 100.00
aes_alert_reset 2.000s 114.871us 1 1 100.00
trigger_clear_test 1 1 100.00
aes_clear 3.000s 88.037us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 7.000s 385.997us 1 1 100.00
reset_recovery 1 1 100.00
aes_alert_reset 2.000s 114.871us 1 1 100.00
stress 1 1 100.00
aes_stress 3.000s 110.964us 1 1 100.00
sideload 2 2 100.00
aes_stress 3.000s 110.964us 1 1 100.00
aes_sideload 4.000s 104.082us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 3.000s 77.426us 1 1 100.00
stress_all 1 1 100.00
aes_stress_all 8.000s 77.424us 1 1 100.00
alert_test 1 1 100.00
aes_alert_test 3.000s 288.878us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 3.000s 96.366us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 3.000s 96.366us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 2.000s 59.049us 1 1 100.00
aes_csr_rw 2.000s 58.449us 1 1 100.00
aes_csr_aliasing 3.000s 91.791us 1 1 100.00
aes_same_csr_outstanding 3.000s 381.016us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 2.000s 59.049us 1 1 100.00
aes_csr_rw 2.000s 58.449us 1 1 100.00
aes_csr_aliasing 3.000s 91.791us 1 1 100.00
aes_same_csr_outstanding 3.000s 381.016us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 1 1 100.00
aes_reseed 4.000s 100.034us 1 1 100.00
fault_inject 2 3 66.67
aes_fi 4.000s 305.249us 0 1 0.00
aes_control_fi 2.000s 48.466us 1 1 100.00
aes_cipher_fi 3.000s 88.919us 1 1 100.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 3.000s 94.000us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 3.000s 94.000us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 3.000s 94.000us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 3.000s 94.000us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 3.000s 189.749us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 4.000s 2804.476us 1 1 100.00
aes_tl_intg_err 3.000s 173.814us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 3.000s 173.814us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
aes_alert_reset 2.000s 114.871us 1 1 100.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 3.000s 94.000us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 3.000s 94.000us 1 1 100.00
sec_cm_main_config_sparse 4 4 100.00
aes_smoke 3.000s 119.520us 1 1 100.00
aes_stress 3.000s 110.964us 1 1 100.00
aes_alert_reset 2.000s 114.871us 1 1 100.00
aes_core_fi 3.000s 139.317us 1 1 100.00
sec_cm_gcm_config_sparse 3 3 100.00
aes_config_error 2.000s 90.816us 1 1 100.00
aes_stress 3.000s 110.964us 1 1 100.00
aes_core_fi 3.000s 139.317us 1 1 100.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 3.000s 94.000us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 2.000s 67.846us 1 1 100.00
aes_stress 3.000s 110.964us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 3.000s 110.964us 1 1 100.00
aes_sideload 4.000s 104.082us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 2.000s 67.846us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 2.000s 67.846us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 2.000s 67.846us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 2.000s 67.846us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 2.000s 67.846us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 3.000s 110.964us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 3.000s 110.964us 1 1 100.00
sec_cm_main_fsm_sparse 0 1 0.00
aes_fi 4.000s 305.249us 0 1 0.00
sec_cm_main_fsm_redun 3 4 75.00
aes_fi 4.000s 305.249us 0 1 0.00
aes_control_fi 2.000s 48.466us 1 1 100.00
aes_cipher_fi 3.000s 88.919us 1 1 100.00
aes_ctr_fi 3.000s 53.411us 1 1 100.00
sec_cm_cipher_fsm_sparse 0 1 0.00
aes_fi 4.000s 305.249us 0 1 0.00
sec_cm_cipher_fsm_redun 2 3 66.67
aes_fi 4.000s 305.249us 0 1 0.00
aes_control_fi 2.000s 48.466us 1 1 100.00
aes_cipher_fi 3.000s 88.919us 1 1 100.00
sec_cm_cipher_ctr_redun 1 1 100.00
aes_cipher_fi 3.000s 88.919us 1 1 100.00
sec_cm_ctr_fsm_sparse 0 1 0.00
aes_fi 4.000s 305.249us 0 1 0.00
sec_cm_ctr_fsm_redun 2 3 66.67
aes_fi 4.000s 305.249us 0 1 0.00
aes_control_fi 2.000s 48.466us 1 1 100.00
aes_ctr_fi 3.000s 53.411us 1 1 100.00
sec_cm_ghash_fsm_sparse 0 1 0.00
aes_fi 4.000s 305.249us 0 1 0.00
sec_cm_ctrl_sparse 3 4 75.00
aes_fi 4.000s 305.249us 0 1 0.00
aes_control_fi 2.000s 48.466us 1 1 100.00
aes_cipher_fi 3.000s 88.919us 1 1 100.00
aes_ctr_fi 3.000s 53.411us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
aes_alert_reset 2.000s 114.871us 1 1 100.00
sec_cm_main_fsm_local_esc 3 4 75.00
aes_fi 4.000s 305.249us 0 1 0.00
aes_control_fi 2.000s 48.466us 1 1 100.00
aes_cipher_fi 3.000s 88.919us 1 1 100.00
aes_ctr_fi 3.000s 53.411us 1 1 100.00
sec_cm_cipher_fsm_local_esc 3 4 75.00
aes_fi 4.000s 305.249us 0 1 0.00
aes_control_fi 2.000s 48.466us 1 1 100.00
aes_cipher_fi 3.000s 88.919us 1 1 100.00
aes_ctr_fi 3.000s 53.411us 1 1 100.00
sec_cm_ctr_fsm_local_esc 2 3 66.67
aes_fi 4.000s 305.249us 0 1 0.00
aes_control_fi 2.000s 48.466us 1 1 100.00
aes_ctr_fi 3.000s 53.411us 1 1 100.00
sec_cm_ghash_fsm_local_esc 0 1 0.00
aes_fi 4.000s 305.249us 0 1 0.00
sec_cm_data_reg_local_esc 2 3 66.67
aes_fi 4.000s 305.249us 0 1 0.00
aes_control_fi 2.000s 48.466us 1 1 100.00
aes_cipher_fi 3.000s 88.919us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 2.000s 16.490us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (aes_scoreboard.sv:926) scoreboard [scoreboard] 1 test run
aes_fi 74158046343739098071269284357846478613487309031120197678176478158699936925635 11956
----| NO FAILURES BUT NUMBER OF EXPECTED MESSAGES DOES NOT MATCH ACTUAL
----| Expected: 3
----| Seen: 1
----| Expected corrupted: 0
UVM_FATAL (aes_base_vseq.sv:87) [aes_stress_all_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) 1 test run
aes_stress_all_with_rand_reset 99739848663685866228699926534377245880154455995799309787775193883609507621436 109
UVM_INFO @ 16490386 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---