Simulation Results: chip

 
06/08/2026 15:30:30 DVSim: v1.50.0 sha: 377160a json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 72.18 %
  • code
  • 81.49 %
  • assert
  • 97.50 %
  • func
  • 37.56 %
  • line
  • 94.35 %
  • branch
  • 93.72 %
  • cond
  • 88.82 %
  • toggle
  • 73.44 %
  • FSM
  • 57.14 %
Validation stages
V1
94.44%
V2
88.45%
V2S
50.00%
V3
65.38%
unmapped
63.64%
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_example_tests 4 4 100.00
chip_sw_example_flash 205.920s 3861.270us 1 1 100.00
chip_sw_example_rom 111.050s 3105.943us 1 1 100.00
chip_sw_example_manufacturer 175.760s 3346.195us 1 1 100.00
chip_sw_example_concurrency 219.190s 2814.472us 1 1 100.00
csr_hw_reset 1 1 100.00
chip_csr_hw_reset 239.900s 5894.628us 1 1 100.00
csr_rw 1 1 100.00
chip_csr_rw 457.870s 6443.033us 1 1 100.00
csr_bit_bash 1 1 100.00
chip_csr_bit_bash 213.060s 4049.909us 1 1 100.00
csr_aliasing 1 1 100.00
chip_csr_aliasing 3983.930s 30742.107us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
chip_csr_mem_rw_with_rand_reset 81.770s 3010.655us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
chip_csr_aliasing 3983.930s 30742.107us 1 1 100.00
chip_csr_rw 457.870s 6443.033us 1 1 100.00
xbar_smoke 1 1 100.00
xbar_smoke 6.730s 172.659us 1 1 100.00
chip_sw_gpio_out 1 1 100.00
chip_sw_gpio 333.410s 4848.767us 1 1 100.00
chip_sw_gpio_in 1 1 100.00
chip_sw_gpio 333.410s 4848.767us 1 1 100.00
chip_sw_gpio_irq 1 1 100.00
chip_sw_gpio 333.410s 4848.767us 1 1 100.00
chip_sw_uart_tx_rx 1 1 100.00
chip_sw_uart_tx_rx 410.600s 5020.956us 1 1 100.00
chip_sw_uart_rx_overflow 4 4 100.00
chip_sw_uart_tx_rx 410.600s 5020.956us 1 1 100.00
chip_sw_uart_tx_rx_idx1 414.090s 5108.632us 1 1 100.00
chip_sw_uart_tx_rx_idx2 433.660s 4651.202us 1 1 100.00
chip_sw_uart_tx_rx_idx3 459.220s 4752.640us 1 1 100.00
chip_sw_uart_baud_rate 1 1 100.00
chip_sw_uart_rand_baudrate 1089.200s 8709.573us 1 1 100.00
chip_sw_uart_tx_rx_alt_clk_freq 2 2 100.00
chip_sw_uart_tx_rx_alt_clk_freq 1042.840s 8455.426us 1 1 100.00
chip_sw_uart_tx_rx_alt_clk_freq_low_speed 373.260s 5011.773us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_pin_mux 1 1 100.00
chip_padctrl_attributes 236.200s 5088.499us 1 1 100.00
chip_padctrl_attributes 1 1 100.00
chip_padctrl_attributes 236.200s 5088.499us 1 1 100.00
chip_sw_sleep_pin_mio_dio_val 1 1 100.00
chip_sw_sleep_pin_mio_dio_val 230.830s 3956.122us 1 1 100.00
chip_sw_sleep_pin_wake 1 1 100.00
chip_sw_sleep_pin_wake 402.520s 6172.473us 1 1 100.00
chip_sw_sleep_pin_retention 1 1 100.00
chip_sw_sleep_pin_retention 221.090s 4400.131us 1 1 100.00
chip_sw_tap_strap_sampling 4 4 100.00
chip_tap_straps_dev 215.970s 4046.458us 1 1 100.00
chip_tap_straps_testunlock0 456.580s 7191.550us 1 1 100.00
chip_tap_straps_rma 284.380s 5021.247us 1 1 100.00
chip_tap_straps_prod 135.310s 2600.360us 1 1 100.00
chip_sw_data_integrity 1 1 100.00
chip_sw_data_integrity_escalation 673.980s 7867.782us 1 1 100.00
chip_sw_instruction_integrity 1 1 100.00
chip_sw_data_integrity_escalation 673.980s 7867.782us 1 1 100.00
chip_sw_ast_clk_outputs 1 1 100.00
chip_sw_ast_clk_outputs 684.110s 9235.735us 1 1 100.00
chip_sw_ast_clk_rst_inputs 0 1 0.00
chip_sw_ast_clk_rst_inputs 901.100s 9889.797us 0 1 0.00
chip_sw_ast_sys_clk_jitter 10 10 100.00
chip_sw_flash_ctrl_ops_jitter_en 383.750s 4315.831us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en 649.150s 6141.861us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 4004.540s 19398.425us 1 1 100.00
chip_sw_aes_enc_jitter_en 228.040s 4159.669us 1 1 100.00
chip_sw_edn_entropy_reqs_jitter 974.080s 9045.967us 1 1 100.00
chip_sw_hmac_enc_jitter_en 233.480s 3466.003us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en 862.660s 9099.807us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en 242.810s 4547.956us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 540.680s 6681.485us 1 1 100.00
chip_sw_clkmgr_jitter 175.280s 3345.490us 1 1 100.00
chip_sw_ast_usb_clk_calib 1 1 100.00
chip_sw_usb_ast_clk_calib 234.740s 4354.468us 1 1 100.00
chip_sw_sensor_ctrl_ast_alerts 2 2 100.00
chip_sw_sensor_ctrl_alert 753.920s 8846.996us 1 1 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 297.110s 4975.118us 1 1 100.00
chip_sw_sensor_ctrl_ast_status 1 1 100.00
chip_sw_sensor_ctrl_status 212.670s 3470.387us 1 1 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 1 1 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 297.110s 4975.118us 1 1 100.00
chip_sw_smoketest 17 17 100.00
chip_sw_flash_scrambling_smoketest 173.640s 2849.451us 1 1 100.00
chip_sw_aes_smoketest 236.820s 2899.588us 1 1 100.00
chip_sw_aon_timer_smoketest 223.920s 3869.367us 1 1 100.00
chip_sw_clkmgr_smoketest 234.250s 3606.887us 1 1 100.00
chip_sw_csrng_smoketest 183.940s 3743.779us 1 1 100.00
chip_sw_entropy_src_smoketest 921.150s 7087.388us 1 1 100.00
chip_sw_gpio_smoketest 267.910s 3971.882us 1 1 100.00
chip_sw_hmac_smoketest 310.280s 4883.657us 1 1 100.00
chip_sw_kmac_smoketest 265.550s 3878.386us 1 1 100.00
chip_sw_otbn_smoketest 1012.770s 6722.805us 1 1 100.00
chip_sw_pwrmgr_smoketest 404.380s 6608.407us 1 1 100.00
chip_sw_pwrmgr_usbdev_smoketest 308.840s 6555.858us 1 1 100.00
chip_sw_rv_plic_smoketest 203.170s 2994.260us 1 1 100.00
chip_sw_rv_timer_smoketest 195.150s 3735.497us 1 1 100.00
chip_sw_rstmgr_smoketest 205.080s 3300.425us 1 1 100.00
chip_sw_sram_ctrl_smoketest 155.950s 3264.129us 1 1 100.00
chip_sw_uart_smoketest 214.570s 4089.337us 1 1 100.00
chip_sw_otp_smoketest 1 1 100.00
chip_sw_otp_ctrl_smoketest 200.230s 3556.455us 1 1 100.00
chip_sw_rom_functests 0 1 0.00
rom_keymgr_functest 390.940s 6556.504us 0 1 0.00
chip_sw_boot 1 1 100.00
chip_sw_uart_tx_rx_bootstrap 9702.600s 60890.107us 1 1 100.00
chip_sw_secure_boot 1 1 100.00
rom_e2e_smoke 3322.660s 15613.151us 1 1 100.00
chip_sw_rom_raw_unlock 0 1 0.00
rom_raw_unlock 775.520s 15597.031us 0 1 0.00
chip_sw_power_idle_load 0 1 0.00
chip_sw_power_idle_load 1180.190s 15825.497us 0 1 0.00
chip_sw_power_sleep_load 0 1 0.00
chip_sw_power_sleep_load 964.100s 15183.279us 0 1 0.00
chip_sw_exit_test_unlocked_bootstrap 1 1 100.00
chip_sw_exit_test_unlocked_bootstrap 7740.010s 55152.600us 1 1 100.00
chip_sw_inject_scramble_seed 1 1 100.00
chip_sw_inject_scramble_seed 8821.500s 57822.867us 1 1 100.00
tl_d_oob_addr_access 0 1 0.00
chip_tl_errors 55.600s 2231.760us 0 1 0.00
tl_d_illegal_access 0 1 0.00
chip_tl_errors 55.600s 2231.760us 0 1 0.00
tl_d_outstanding_access 4 4 100.00
chip_csr_aliasing 3983.930s 30742.107us 1 1 100.00
chip_same_csr_outstanding 2707.510s 27351.367us 1 1 100.00
chip_csr_hw_reset 239.900s 5894.628us 1 1 100.00
chip_csr_rw 457.870s 6443.033us 1 1 100.00
tl_d_partial_access 4 4 100.00
chip_csr_aliasing 3983.930s 30742.107us 1 1 100.00
chip_same_csr_outstanding 2707.510s 27351.367us 1 1 100.00
chip_csr_hw_reset 239.900s 5894.628us 1 1 100.00
chip_csr_rw 457.870s 6443.033us 1 1 100.00
xbar_base_random_sequence 1 1 100.00
xbar_random 56.070s 2024.031us 1 1 100.00
xbar_random_delay 6 6 100.00
xbar_smoke_zero_delays 5.810s 49.061us 1 1 100.00
xbar_smoke_large_delays 42.260s 6907.371us 1 1 100.00
xbar_smoke_slow_rsp 44.860s 4388.151us 1 1 100.00
xbar_random_zero_delays 13.350s 183.943us 1 1 100.00
xbar_random_large_delays 24.360s 2527.374us 1 1 100.00
xbar_random_slow_rsp 43.910s 4359.308us 1 1 100.00
xbar_unmapped_address 2 2 100.00
xbar_unmapped_addr 21.590s 709.918us 1 1 100.00
xbar_error_and_unmapped_addr 25.550s 824.357us 1 1 100.00
xbar_error_cases 2 2 100.00
xbar_error_random 18.400s 594.601us 1 1 100.00
xbar_error_and_unmapped_addr 25.550s 824.357us 1 1 100.00
xbar_all_access_same_device 2 2 100.00
xbar_access_same_device 34.790s 1281.117us 1 1 100.00
xbar_access_same_device_slow_rsp 200.430s 21582.548us 1 1 100.00
xbar_all_hosts_use_same_source_id 1 1 100.00
xbar_same_source 18.710s 764.759us 1 1 100.00
xbar_stress_all 2 2 100.00
xbar_stress_all 118.940s 3965.078us 1 1 100.00
xbar_stress_all_with_error 112.040s 4355.784us 1 1 100.00
xbar_stress_with_reset 2 2 100.00
xbar_stress_all_with_rand_reset 65.850s 177.851us 1 1 100.00
xbar_stress_all_with_reset_error 144.980s 854.840us 1 1 100.00
rom_e2e_smoke 1 1 100.00
rom_e2e_smoke 3322.660s 15613.151us 1 1 100.00
rom_e2e_shutdown_output 1 1 100.00
rom_e2e_shutdown_output 3016.910s 36465.313us 1 1 100.00
rom_e2e_shutdown_exception_c 1 1 100.00
rom_e2e_shutdown_exception_c 3383.930s 16777.868us 1 1 100.00
rom_e2e_boot_policy_valid 15 15 100.00
rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 2539.400s 11236.507us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_good_dev 3326.550s 15418.773us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_good_prod 3408.560s 16592.554us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_good_prod_end 3569.410s 19089.204us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_good_rma 3306.800s 17507.426us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 2628.630s 12720.680us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_bad_dev 3263.970s 16051.759us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_bad_prod 3364.450s 18730.334us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_bad_prod_end 3537.870s 17625.599us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_bad_rma 3301.390s 15710.629us 1 1 100.00
rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 4622.750s 19159.390us 1 1 100.00
rom_e2e_boot_policy_valid_a_bad_b_good_dev 5983.210s 24668.475us 1 1 100.00
rom_e2e_boot_policy_valid_a_bad_b_good_prod 6023.420s 23972.318us 1 1 100.00
rom_e2e_boot_policy_valid_a_bad_b_good_prod_end 6164.180s 26370.023us 1 1 100.00
rom_e2e_boot_policy_valid_a_bad_b_good_rma 5909.430s 24131.615us 1 1 100.00
rom_e2e_sigverify_always 15 15 100.00
rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 4442.220s 20350.583us 1 1 100.00
rom_e2e_sigverify_always_a_bad_b_bad_dev 5977.310s 24522.756us 1 1 100.00
rom_e2e_sigverify_always_a_bad_b_bad_prod 5841.460s 23902.683us 1 1 100.00
rom_e2e_sigverify_always_a_bad_b_bad_prod_end 6065.140s 24307.550us 1 1 100.00
rom_e2e_sigverify_always_a_bad_b_bad_rma 5929.980s 22866.276us 1 1 100.00
rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 2340.940s 11628.599us 1 1 100.00
rom_e2e_sigverify_always_a_bad_b_nothing_dev 3152.420s 20616.403us 1 1 100.00
rom_e2e_sigverify_always_a_bad_b_nothing_prod 3072.050s 14763.998us 1 1 100.00
rom_e2e_sigverify_always_a_bad_b_nothing_prod_end 3344.170s 16102.844us 1 1 100.00
rom_e2e_sigverify_always_a_bad_b_nothing_rma 3020.510s 13462.186us 1 1 100.00
rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 2447.020s 11725.831us 1 1 100.00
rom_e2e_sigverify_always_a_nothing_b_bad_dev 3457.380s 16923.618us 1 1 100.00
rom_e2e_sigverify_always_a_nothing_b_bad_prod 3205.040s 15268.430us 1 1 100.00
rom_e2e_sigverify_always_a_nothing_b_bad_prod_end 3233.700s 14833.995us 1 1 100.00
rom_e2e_sigverify_always_a_nothing_b_bad_rma 2985.810s 14415.518us 1 1 100.00
rom_e2e_asm_init 5 5 100.00
rom_e2e_asm_init_test_unlocked0 2659.270s 14668.612us 1 1 100.00
rom_e2e_asm_init_dev 3367.230s 15857.031us 1 1 100.00
rom_e2e_asm_init_prod 3239.010s 17134.575us 1 1 100.00
rom_e2e_asm_init_prod_end 3423.710s 16611.678us 1 1 100.00
rom_e2e_asm_init_rma 3024.030s 15084.987us 1 1 100.00
rom_e2e_keymgr_init 1 3 33.33
rom_e2e_keymgr_init_rom_ext_meas 6839.500s 30156.793us 1 1 100.00
rom_e2e_keymgr_init_rom_ext_no_meas 3523.860s 18370.068us 0 1 0.00
rom_e2e_keymgr_init_rom_ext_invalid_meas 3363.000s 16897.641us 0 1 0.00
rom_e2e_static_critical 1 1 100.00
rom_e2e_static_critical 3858.680s 18503.954us 1 1 100.00
chip_sw_adc_ctrl_debug_cable_irq 0 1 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 3600.172s 0.000us 0 1 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 0 1 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 3600.172s 0.000us 0 1 0.00
chip_sw_aes_enc 2 2 100.00
chip_sw_aes_enc 270.700s 4504.647us 1 1 100.00
chip_sw_aes_enc_jitter_en 228.040s 4159.669us 1 1 100.00
chip_sw_aes_entropy 1 1 100.00
chip_sw_aes_entropy 168.760s 4178.583us 1 1 100.00
chip_sw_aes_idle 1 1 100.00
chip_sw_aes_idle 202.920s 3686.420us 1 1 100.00
chip_sw_aes_sideload 1 1 100.00
chip_sw_keymgr_sideload_aes 988.190s 8782.131us 1 1 100.00
chip_sw_alert_handler_alerts 0 1 0.00
chip_sw_alert_test 250.960s 3409.457us 0 1 0.00
chip_sw_alert_handler_escalations 1 1 100.00
chip_sw_alert_handler_escalation 335.840s 5278.082us 1 1 100.00
chip_sw_all_escalation_resets 1 1 100.00
chip_sw_all_escalation_resets 475.910s 6787.579us 1 1 100.00
chip_sw_alert_handler_irqs 3 3 100.00
chip_plic_all_irqs_0 542.700s 5441.567us 1 1 100.00
chip_plic_all_irqs_10 306.910s 3691.963us 1 1 100.00
chip_plic_all_irqs_20 402.460s 4868.394us 1 1 100.00
chip_sw_alert_handler_entropy 1 1 100.00
chip_sw_alert_handler_entropy 242.070s 4360.923us 1 1 100.00
chip_sw_alert_handler_crashdump 1 1 100.00
chip_sw_rstmgr_alert_info 1461.890s 16946.843us 1 1 100.00
chip_sw_alert_handler_ping_timeout 1 1 100.00
chip_sw_alert_handler_ping_timeout 326.830s 4807.479us 1 1 100.00
chip_sw_alert_handler_lpg_sleep_mode_alerts 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_alerts 140.710s 3062.593us 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_pings 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_pings 14400.143s 0.000us 0 1 0.00
chip_sw_alert_handler_lpg_clock_off 1 1 100.00
chip_sw_alert_handler_lpg_clkoff 702.720s 6746.725us 1 1 100.00
chip_sw_alert_handler_lpg_reset_toggle 1 1 100.00
chip_sw_alert_handler_lpg_reset_toggle 777.920s 6342.532us 1 1 100.00
chip_sw_alert_handler_ping_ok 1 1 100.00
chip_sw_alert_handler_ping_ok 898.900s 9007.928us 1 1 100.00
chip_sw_alert_handler_reverse_ping_in_deep_sleep 1 1 100.00
chip_sw_alert_handler_reverse_ping_in_deep_sleep 9792.810s 255819.389us 1 1 100.00
chip_sw_aon_timer_wakeup_irq 1 1 100.00
chip_sw_aon_timer_irq 297.680s 4617.165us 1 1 100.00
chip_sw_aon_timer_sleep_wakeup 1 1 100.00
chip_sw_pwrmgr_smoketest 404.380s 6608.407us 1 1 100.00
chip_sw_aon_timer_wdog_bark_irq 1 1 100.00
chip_sw_aon_timer_irq 297.680s 4617.165us 1 1 100.00
chip_sw_aon_timer_wdog_bite_reset 0 1 0.00
chip_sw_aon_timer_wdog_bite_reset 558.110s 9041.026us 0 1 0.00
chip_sw_aon_timer_sleep_wdog_bite_reset 0 1 0.00
chip_sw_aon_timer_wdog_bite_reset 558.110s 9041.026us 0 1 0.00
chip_sw_aon_timer_sleep_wdog_sleep_pause 1 1 100.00
chip_sw_aon_timer_sleep_wdog_sleep_pause 380.740s 8889.804us 1 1 100.00
chip_sw_aon_timer_wdog_lc_escalate 1 1 100.00
chip_sw_aon_timer_wdog_lc_escalate 477.860s 6797.462us 1 1 100.00
chip_sw_clkmgr_idle_trans 4 4 100.00
chip_sw_otbn_randomness 688.600s 6414.518us 1 1 100.00
chip_sw_aes_idle 202.920s 3686.420us 1 1 100.00
chip_sw_hmac_enc_idle 196.280s 2869.135us 1 1 100.00
chip_sw_kmac_idle 202.030s 4045.058us 1 1 100.00
chip_sw_clkmgr_off_trans 4 4 100.00
chip_sw_clkmgr_off_aes_trans 392.050s 4833.653us 1 1 100.00
chip_sw_clkmgr_off_hmac_trans 312.090s 5364.534us 1 1 100.00
chip_sw_clkmgr_off_kmac_trans 321.290s 6155.517us 1 1 100.00
chip_sw_clkmgr_off_otbn_trans 350.020s 5392.304us 1 1 100.00
chip_sw_clkmgr_off_peri 1 1 100.00
chip_sw_clkmgr_off_peri 1140.600s 12513.174us 1 1 100.00
chip_sw_clkmgr_div 7 7 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 472.830s 4978.315us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 483.850s 5800.791us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 514.390s 5310.771us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 467.990s 5920.300us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_rma 493.880s 4993.367us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_rma 474.360s 5194.729us 1 1 100.00
chip_sw_ast_clk_outputs 684.110s 9235.735us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_lc 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_lc 456.850s 8739.909us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw 2 2 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 514.390s 5310.771us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 467.990s 5920.300us 1 1 100.00
chip_sw_clkmgr_jitter 10 10 100.00
chip_sw_flash_ctrl_ops_jitter_en 383.750s 4315.831us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en 649.150s 6141.861us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 4004.540s 19398.425us 1 1 100.00
chip_sw_aes_enc_jitter_en 228.040s 4159.669us 1 1 100.00
chip_sw_edn_entropy_reqs_jitter 974.080s 9045.967us 1 1 100.00
chip_sw_hmac_enc_jitter_en 233.480s 3466.003us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en 862.660s 9099.807us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en 242.810s 4547.956us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 540.680s 6681.485us 1 1 100.00
chip_sw_clkmgr_jitter 175.280s 3345.490us 1 1 100.00
chip_sw_clkmgr_extended_range 11 11 100.00
chip_sw_clkmgr_jitter_reduced_freq 233.870s 4131.063us 1 1 100.00
chip_sw_flash_ctrl_ops_jitter_en_reduced_freq 391.660s 4978.971us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en_reduced_freq 694.760s 7888.171us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq 4381.380s 26116.539us 1 1 100.00
chip_sw_aes_enc_jitter_en_reduced_freq 176.900s 3330.238us 1 1 100.00
chip_sw_hmac_enc_jitter_en_reduced_freq 199.550s 3388.300us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en_reduced_freq 925.590s 9263.258us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en_reduced_freq 206.800s 3054.108us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq 450.080s 5754.903us 1 1 100.00
chip_sw_flash_init_reduced_freq 1733.290s 32699.998us 1 1 100.00
chip_sw_csrng_edn_concurrency_reduced_freq 4598.460s 32572.548us 1 1 100.00
chip_sw_clkmgr_deep_sleep_frequency 1 1 100.00
chip_sw_ast_clk_outputs 684.110s 9235.735us 1 1 100.00
chip_sw_clkmgr_sleep_frequency 1 1 100.00
chip_sw_clkmgr_sleep_frequency 387.580s 5230.522us 1 1 100.00
chip_sw_clkmgr_reset_frequency 1 1 100.00
chip_sw_clkmgr_reset_frequency 318.750s 3591.035us 1 1 100.00
chip_sw_clkmgr_escalation_reset 1 1 100.00
chip_sw_all_escalation_resets 475.910s 6787.579us 1 1 100.00
chip_sw_clkmgr_alert_handler_clock_enables 1 1 100.00
chip_sw_alert_handler_lpg_clkoff 702.720s 6746.725us 1 1 100.00
chip_sw_csrng_edn_cmd 1 1 100.00
chip_sw_entropy_src_csrng 2712.890s 24987.089us 1 1 100.00
chip_sw_csrng_fuse_en_sw_app_read 1 1 100.00
chip_sw_csrng_fuse_en_sw_app_read_test 307.080s 6325.532us 1 1 100.00
chip_sw_csrng_lc_hw_debug_en 1 1 100.00
chip_sw_csrng_lc_hw_debug_en_test 613.260s 8303.420us 1 1 100.00
chip_sw_csrng_known_answer_tests 1 1 100.00
chip_sw_csrng_kat_test 257.620s 4618.553us 1 1 100.00
chip_sw_edn_entropy_reqs 3 3 100.00
chip_sw_csrng_edn_concurrency 2795.480s 15303.058us 1 1 100.00
chip_sw_entropy_src_ast_rng_req 207.830s 3683.706us 1 1 100.00
chip_sw_edn_entropy_reqs 870.540s 6509.717us 1 1 100.00
chip_sw_entropy_src_ast_rng_req 1 1 100.00
chip_sw_entropy_src_ast_rng_req 207.830s 3683.706us 1 1 100.00
chip_sw_entropy_src_csrng 1 1 100.00
chip_sw_entropy_src_csrng 2712.890s 24987.089us 1 1 100.00
chip_sw_entropy_src_known_answer_tests 1 1 100.00
chip_sw_entropy_src_kat_test 193.930s 4033.315us 1 1 100.00
chip_sw_flash_init 1 1 100.00
chip_sw_flash_init 1323.280s 26580.347us 1 1 100.00
chip_sw_flash_host_access 2 2 100.00
chip_sw_flash_ctrl_access 653.470s 5581.074us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en 649.150s 6141.861us 1 1 100.00
chip_sw_flash_ctrl_ops 2 2 100.00
chip_sw_flash_ctrl_ops 456.410s 4848.186us 1 1 100.00
chip_sw_flash_ctrl_ops_jitter_en 383.750s 4315.831us 1 1 100.00
chip_sw_flash_rma_unlocked 1 1 100.00
chip_sw_flash_rma_unlocked 4344.560s 45879.254us 1 1 100.00
chip_sw_flash_scramble 1 1 100.00
chip_sw_flash_init 1323.280s 26580.347us 1 1 100.00
chip_sw_flash_idle_low_power 1 1 100.00
chip_sw_flash_ctrl_idle_low_power 264.480s 3919.429us 1 1 100.00
chip_sw_flash_keymgr_seeds 1 1 100.00
chip_sw_keymgr_key_derivation 2042.480s 14501.981us 1 1 100.00
chip_sw_flash_lc_creator_seed_sw_rw_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 196.190s 3003.861us 0 1 0.00
chip_sw_flash_creator_seed_wipe_on_rma 1 1 100.00
chip_sw_flash_rma_unlocked 4344.560s 45879.254us 1 1 100.00
chip_sw_flash_lc_owner_seed_sw_rw_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 196.190s 3003.861us 0 1 0.00
chip_sw_flash_lc_iso_part_sw_rd_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 196.190s 3003.861us 0 1 0.00
chip_sw_flash_lc_iso_part_sw_wr_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 196.190s 3003.861us 0 1 0.00
chip_sw_flash_lc_seed_hw_rd_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 196.190s 3003.861us 0 1 0.00
chip_sw_flash_lc_escalate_en 1 1 100.00
chip_sw_all_escalation_resets 475.910s 6787.579us 1 1 100.00
chip_sw_flash_prim_tl_access 1 1 100.00
chip_prim_tl_access 213.070s 8862.314us 1 1 100.00
chip_sw_flash_ctrl_clock_freqs 1 1 100.00
chip_sw_flash_ctrl_clock_freqs 649.180s 5542.329us 1 1 100.00
chip_sw_flash_ctrl_escalation_reset 1 1 100.00
chip_sw_flash_crash_alert 575.970s 7668.154us 1 1 100.00
chip_sw_flash_ctrl_write_clear 1 1 100.00
chip_sw_flash_crash_alert 575.970s 7668.154us 1 1 100.00
chip_sw_hmac_enc 2 2 100.00
chip_sw_hmac_enc 188.780s 3437.045us 1 1 100.00
chip_sw_hmac_enc_jitter_en 233.480s 3466.003us 1 1 100.00
chip_sw_hmac_idle 1 1 100.00
chip_sw_hmac_enc_idle 196.280s 2869.135us 1 1 100.00
chip_sw_hmac_all_configurations 1 1 100.00
chip_sw_hmac_oneshot 1489.050s 9815.946us 1 1 100.00
chip_sw_hmac_multistream_mode 0 1 0.00
chip_sw_hmac_multistream 1877.880s 12026.782us 0 1 0.00
chip_sw_i2c_host_tx_rx 3 3 100.00
chip_sw_i2c_host_tx_rx 529.320s 5531.004us 1 1 100.00
chip_sw_i2c_host_tx_rx_idx1 457.400s 5672.907us 1 1 100.00
chip_sw_i2c_host_tx_rx_idx2 450.550s 6074.381us 1 1 100.00
chip_sw_i2c_device_tx_rx 1 1 100.00
chip_sw_i2c_device_tx_rx 432.480s 5460.300us 1 1 100.00
chip_sw_keymgr_key_derivation 2 2 100.00
chip_sw_keymgr_key_derivation 2042.480s 14501.981us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en 862.660s 9099.807us 1 1 100.00
chip_sw_keymgr_sideload_kmac 1 1 100.00
chip_sw_keymgr_sideload_kmac 1909.730s 12689.397us 1 1 100.00
chip_sw_keymgr_sideload_aes 1 1 100.00
chip_sw_keymgr_sideload_aes 988.190s 8782.131us 1 1 100.00
chip_sw_keymgr_sideload_otbn 0 1 0.00
chip_sw_keymgr_sideload_otbn 5112.560s 20026.802us 0 1 0.00
chip_sw_kmac_enc 3 3 100.00
chip_sw_kmac_mode_cshake 233.480s 3981.865us 1 1 100.00
chip_sw_kmac_mode_kmac 196.920s 3348.616us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en 242.810s 4547.956us 1 1 100.00
chip_sw_kmac_app_keymgr 1 1 100.00
chip_sw_keymgr_key_derivation 2042.480s 14501.981us 1 1 100.00
chip_sw_kmac_app_lc 1 1 100.00
chip_sw_lc_ctrl_transition 1066.250s 18182.273us 1 1 100.00
chip_sw_kmac_app_rom 1 1 100.00
chip_sw_kmac_app_rom 262.440s 4224.808us 1 1 100.00
chip_sw_kmac_entropy 1 1 100.00
chip_sw_kmac_entropy 1009.630s 8209.713us 1 1 100.00
chip_sw_kmac_idle 1 1 100.00
chip_sw_kmac_idle 202.030s 4045.058us 1 1 100.00
chip_sw_lc_ctrl_alert_handler_escalation 1 1 100.00
chip_sw_alert_handler_escalation 335.840s 5278.082us 1 1 100.00
chip_sw_lc_ctrl_jtag_access 3 3 100.00
chip_tap_straps_dev 215.970s 4046.458us 1 1 100.00
chip_tap_straps_rma 284.380s 5021.247us 1 1 100.00
chip_tap_straps_prod 135.310s 2600.360us 1 1 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 1 1 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 222.930s 3699.477us 1 1 100.00
chip_sw_lc_ctrl_init 1 1 100.00
chip_sw_lc_ctrl_transition 1066.250s 18182.273us 1 1 100.00
chip_sw_lc_ctrl_transitions 1 1 100.00
chip_sw_lc_ctrl_transition 1066.250s 18182.273us 1 1 100.00
chip_sw_lc_ctrl_kmac_req 1 1 100.00
chip_sw_lc_ctrl_transition 1066.250s 18182.273us 1 1 100.00
chip_sw_lc_ctrl_key_div 1 1 100.00
chip_sw_keymgr_key_derivation_prod 1413.800s 11073.143us 1 1 100.00
chip_sw_lc_ctrl_broadcast 19 22 86.36
chip_sw_flash_ctrl_lc_rw_en 196.190s 3003.861us 0 1 0.00
chip_sw_flash_rma_unlocked 4344.560s 45879.254us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_test_unlocked0 237.680s 3900.087us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_dev 510.320s 7801.101us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_prod 619.950s 8186.988us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_rma 574.500s 8495.815us 0 1 0.00
chip_sw_lc_ctrl_transition 1066.250s 18182.273us 1 1 100.00
chip_sw_keymgr_key_derivation 2042.480s 14501.981us 1 1 100.00
chip_sw_rom_ctrl_integrity_check 504.160s 9208.132us 1 1 100.00
chip_sw_sram_ctrl_execution_main 517.520s 8911.266us 1 1 100.00
chip_prim_tl_access 213.070s 8862.314us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_lc 456.850s 8739.909us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 472.830s 4978.315us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 483.850s 5800.791us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 514.390s 5310.771us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 467.990s 5920.300us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_rma 493.880s 4993.367us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_rma 474.360s 5194.729us 1 1 100.00
chip_tap_straps_dev 215.970s 4046.458us 1 1 100.00
chip_tap_straps_rma 284.380s 5021.247us 1 1 100.00
chip_tap_straps_prod 135.310s 2600.360us 1 1 100.00
chip_rv_dm_lc_disabled 322.180s 11803.814us 0 1 0.00
chip_lc_scrap 4 4 100.00
chip_sw_lc_ctrl_rma_to_scrap 204.340s 4379.794us 1 1 100.00
chip_sw_lc_ctrl_raw_to_scrap 111.780s 3356.374us 1 1 100.00
chip_sw_lc_ctrl_test_locked0_to_scrap 136.570s 3723.891us 1 1 100.00
chip_sw_lc_ctrl_rand_to_scrap 133.200s 3353.925us 1 1 100.00
chip_lc_test_locked 1 2 50.00
chip_sw_lc_walkthrough_testunlocks 2308.920s 36824.791us 1 1 100.00
chip_rv_dm_lc_disabled 322.180s 11803.814us 0 1 0.00
chip_sw_lc_walkthrough 2 5 40.00
chip_sw_lc_walkthrough_dev 787.870s 13188.764us 0 1 0.00
chip_sw_lc_walkthrough_prod 834.600s 12015.019us 0 1 0.00
chip_sw_lc_walkthrough_prodend 975.670s 12750.952us 1 1 100.00
chip_sw_lc_walkthrough_rma 381.690s 6031.407us 0 1 0.00
chip_sw_lc_walkthrough_testunlocks 2308.920s 36824.791us 1 1 100.00
chip_sw_lc_ctrl_volatile_raw_unlock 3 3 100.00
chip_sw_lc_ctrl_volatile_raw_unlock 91.900s 2879.733us 1 1 100.00
chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz 93.950s 3699.881us 1 1 100.00
rom_volatile_raw_unlock 85.400s 3562.225us 1 1 100.00
chip_sw_otbn_op 2 2 100.00
chip_sw_otbn_ecdsa_op_irq 3835.520s 17653.458us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 4004.540s 19398.425us 1 1 100.00
chip_sw_otbn_rnd_entropy 1 1 100.00
chip_sw_otbn_randomness 688.600s 6414.518us 1 1 100.00
chip_sw_otbn_urnd_entropy 1 1 100.00
chip_sw_otbn_randomness 688.600s 6414.518us 1 1 100.00
chip_sw_otbn_idle 1 1 100.00
chip_sw_otbn_randomness 688.600s 6414.518us 1 1 100.00
chip_sw_otbn_mem_scramble 1 1 100.00
chip_sw_otbn_mem_scramble 326.020s 3394.493us 1 1 100.00
chip_otp_ctrl_init 1 1 100.00
chip_sw_lc_ctrl_transition 1066.250s 18182.273us 1 1 100.00
chip_sw_otp_ctrl_keys 5 5 100.00
chip_sw_flash_init 1323.280s 26580.347us 1 1 100.00
chip_sw_otbn_mem_scramble 326.020s 3394.493us 1 1 100.00
chip_sw_keymgr_key_derivation 2042.480s 14501.981us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access 412.000s 5489.704us 1 1 100.00
chip_sw_rv_core_ibex_icache_invalidate 189.440s 2906.505us 1 1 100.00
chip_sw_otp_ctrl_entropy 5 5 100.00
chip_sw_flash_init 1323.280s 26580.347us 1 1 100.00
chip_sw_otbn_mem_scramble 326.020s 3394.493us 1 1 100.00
chip_sw_keymgr_key_derivation 2042.480s 14501.981us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access 412.000s 5489.704us 1 1 100.00
chip_sw_rv_core_ibex_icache_invalidate 189.440s 2906.505us 1 1 100.00
chip_sw_otp_ctrl_program 1 1 100.00
chip_sw_lc_ctrl_transition 1066.250s 18182.273us 1 1 100.00
chip_sw_otp_ctrl_program_error 1 1 100.00
chip_sw_lc_ctrl_program_error 326.530s 4449.649us 1 1 100.00
chip_sw_otp_ctrl_hw_cfg0 1 1 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 222.930s 3699.477us 1 1 100.00
chip_sw_otp_ctrl_lc_signals 5 6 83.33
chip_sw_otp_ctrl_lc_signals_test_unlocked0 237.680s 3900.087us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_dev 510.320s 7801.101us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_prod 619.950s 8186.988us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_rma 574.500s 8495.815us 0 1 0.00
chip_sw_lc_ctrl_transition 1066.250s 18182.273us 1 1 100.00
chip_prim_tl_access 213.070s 8862.314us 1 1 100.00
chip_sw_otp_prim_tl_access 1 1 100.00
chip_prim_tl_access 213.070s 8862.314us 1 1 100.00
chip_sw_otp_ctrl_dai_lock 1 1 100.00
chip_sw_otp_ctrl_dai_lock 919.820s 9188.410us 1 1 100.00
chip_sw_pwrmgr_external_full_reset 0 1 0.00
chip_sw_pwrmgr_full_aon_reset 211.600s 5281.458us 0 1 0.00
chip_sw_pwrmgr_random_sleep_all_wake_ups 1 1 100.00
chip_sw_pwrmgr_random_sleep_all_wake_ups 1570.460s 33031.674us 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_wake_ups 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_wake_ups 302.300s 8020.117us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_por_reset 0 1 0.00
chip_sw_pwrmgr_deep_sleep_por_reset 475.790s 8966.834us 0 1 0.00
chip_sw_pwrmgr_normal_sleep_por_reset 1 1 100.00
chip_sw_pwrmgr_normal_sleep_por_reset 402.920s 7222.494us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_all_wake_ups 1 1 100.00
chip_sw_pwrmgr_deep_sleep_all_wake_ups 1267.330s 31262.266us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 0 2 0.00
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 501.490s 11697.409us 0 1 0.00
chip_sw_aon_timer_wdog_bite_reset 558.110s 9041.026us 0 1 0.00
chip_sw_pwrmgr_normal_sleep_all_reset_reqs 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_reset_reqs 1245.970s 13912.305us 1 1 100.00
chip_sw_pwrmgr_wdog_reset 1 1 100.00
chip_sw_pwrmgr_wdog_reset 431.900s 5521.628us 1 1 100.00
chip_sw_pwrmgr_power_glitch_reset 0 1 0.00
chip_sw_pwrmgr_full_aon_reset 211.600s 5281.458us 0 1 0.00
chip_sw_pwrmgr_main_power_glitch_reset 1 1 100.00
chip_sw_pwrmgr_main_power_glitch_reset 287.660s 5447.135us 1 1 100.00
chip_sw_pwrmgr_random_sleep_power_glitch_reset 0 1 0.00
chip_sw_pwrmgr_random_sleep_power_glitch_reset 1333.570s 25621.480us 0 1 0.00
chip_sw_pwrmgr_deep_sleep_power_glitch_reset 1 1 100.00
chip_sw_pwrmgr_deep_sleep_power_glitch_reset 352.510s 7266.802us 1 1 100.00
chip_sw_pwrmgr_sleep_power_glitch_reset 0 1 0.00
chip_sw_pwrmgr_sleep_power_glitch_reset 232.650s 4038.208us 0 1 0.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 0 1 0.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 270.980s 6604.620us 0 1 0.00
chip_sw_pwrmgr_sysrst_ctrl_reset 2 2 100.00
chip_sw_pwrmgr_sysrst_ctrl_reset 1002.270s 9583.104us 1 1 100.00
chip_sw_pwrmgr_all_reset_reqs 1346.570s 17542.666us 1 1 100.00
chip_sw_pwrmgr_b2b_sleep_reset_req 1 1 100.00
chip_sw_pwrmgr_b2b_sleep_reset_req 2191.720s 29327.320us 1 1 100.00
chip_sw_pwrmgr_sleep_disabled 1 1 100.00
chip_sw_pwrmgr_sleep_disabled 161.520s 3151.892us 1 1 100.00
chip_sw_pwrmgr_escalation_reset 1 1 100.00
chip_sw_all_escalation_resets 475.910s 6787.579us 1 1 100.00
chip_sw_rom_access 1 1 100.00
chip_sw_rom_ctrl_integrity_check 504.160s 9208.132us 1 1 100.00
chip_sw_rom_ctrl_integrity_check 1 1 100.00
chip_sw_rom_ctrl_integrity_check 504.160s 9208.132us 1 1 100.00
chip_sw_rstmgr_non_sys_reset_info 3 4 75.00
chip_sw_pwrmgr_all_reset_reqs 1346.570s 17542.666us 1 1 100.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 270.980s 6604.620us 0 1 0.00
chip_sw_pwrmgr_wdog_reset 431.900s 5521.628us 1 1 100.00
chip_sw_pwrmgr_smoketest 404.380s 6608.407us 1 1 100.00
chip_sw_rstmgr_sys_reset_info 1 1 100.00
chip_rv_dm_ndm_reset_req 398.280s 5024.473us 1 1 100.00
chip_sw_rstmgr_cpu_info 1 1 100.00
chip_sw_rstmgr_cpu_info 650.050s 9466.419us 1 1 100.00
chip_sw_rstmgr_sw_req_reset 1 1 100.00
chip_sw_rstmgr_sw_req 429.920s 5501.159us 1 1 100.00
chip_sw_rstmgr_alert_info 1 1 100.00
chip_sw_rstmgr_alert_info 1461.890s 16946.843us 1 1 100.00
chip_sw_rstmgr_sw_rst 1 1 100.00
chip_sw_rstmgr_sw_rst 184.320s 3709.013us 1 1 100.00
chip_sw_rstmgr_escalation_reset 1 1 100.00
chip_sw_all_escalation_resets 475.910s 6787.579us 1 1 100.00
chip_sw_rstmgr_alert_handler_reset_enables 1 1 100.00
chip_sw_alert_handler_lpg_reset_toggle 777.920s 6342.532us 1 1 100.00
chip_sw_nmi_irq 1 1 100.00
chip_sw_rv_core_ibex_nmi_irq 479.440s 4923.034us 1 1 100.00
chip_sw_rv_core_ibex_rnd 1 1 100.00
chip_sw_rv_core_ibex_rnd 573.710s 4766.894us 1 1 100.00
chip_sw_rv_core_ibex_address_translation 1 1 100.00
chip_sw_rv_core_ibex_address_translation 234.830s 4104.115us 1 1 100.00
chip_sw_rv_core_ibex_icache_scrambled_access 1 1 100.00
chip_sw_rv_core_ibex_icache_invalidate 189.440s 2906.505us 1 1 100.00
chip_sw_rv_core_ibex_fault_dump 1 1 100.00
chip_sw_rstmgr_cpu_info 650.050s 9466.419us 1 1 100.00
chip_sw_rv_core_ibex_double_fault 1 1 100.00
chip_sw_rstmgr_cpu_info 650.050s 9466.419us 1 1 100.00
chip_sw_rv_core_ibex_mcounteren_writable 1 1 100.00
chip_sw_rv_core_ibex_mcounteren_writable 186.900s 4095.365us 1 1 100.00
chip_jtag_csr_rw 1 1 100.00
chip_jtag_csr_rw 1446.860s 18120.274us 1 1 100.00
chip_jtag_mem_access 1 1 100.00
chip_jtag_mem_access 1186.290s 17254.239us 1 1 100.00
chip_rv_dm_ndm_reset_req 1 1 100.00
chip_rv_dm_ndm_reset_req 398.280s 5024.473us 1 1 100.00
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 0 1 0.00
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 268.200s 3873.298us 0 1 0.00
chip_rv_dm_access_after_wakeup 0 1 0.00
chip_sw_rv_dm_access_after_wakeup 1333.170s 14202.250us 0 1 0.00
chip_sw_rv_dm_jtag_tap_sel 1 1 100.00
chip_tap_straps_rma 284.380s 5021.247us 1 1 100.00
chip_rv_dm_lc_disabled 0 1 0.00
chip_rv_dm_lc_disabled 322.180s 11803.814us 0 1 0.00
chip_sw_plic_all_irqs 3 3 100.00
chip_plic_all_irqs_0 542.700s 5441.567us 1 1 100.00
chip_plic_all_irqs_10 306.910s 3691.963us 1 1 100.00
chip_plic_all_irqs_20 402.460s 4868.394us 1 1 100.00
chip_sw_plic_sw_irq 1 1 100.00
chip_sw_plic_sw_irq 230.770s 3884.977us 1 1 100.00
chip_sw_timer 1 1 100.00
chip_sw_rv_timer_irq 186.770s 3258.335us 1 1 100.00
chip_sw_spi_device_flash_mode 1 1 100.00
rom_e2e_smoke 3322.660s 15613.151us 1 1 100.00
chip_sw_spi_device_pass_through 1 1 100.00
chip_sw_spi_device_pass_through 528.300s 7356.920us 1 1 100.00
chip_sw_spi_device_pass_through_collision 0 1 0.00
chip_sw_spi_device_pass_through_collision 286.330s 4412.777us 0 1 0.00
chip_sw_spi_device_tpm 1 1 100.00
chip_sw_spi_device_tpm 281.790s 3938.644us 1 1 100.00
chip_sw_spi_host_tx_rx 1 1 100.00
chip_sw_spi_host_tx_rx 200.310s 3695.071us 1 1 100.00
chip_sw_sram_scrambled_access 2 2 100.00
chip_sw_sram_ctrl_scrambled_access 412.000s 5489.704us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 540.680s 6681.485us 1 1 100.00
chip_sw_sleep_sram_ret_contents 2 2 100.00
chip_sw_sleep_sram_ret_contents_no_scramble 628.930s 10879.996us 1 1 100.00
chip_sw_sleep_sram_ret_contents_scramble 590.080s 8859.562us 1 1 100.00
chip_sw_sram_execution 1 1 100.00
chip_sw_sram_ctrl_execution_main 517.520s 8911.266us 1 1 100.00
chip_sw_sram_lc_escalation 2 2 100.00
chip_sw_all_escalation_resets 475.910s 6787.579us 1 1 100.00
chip_sw_data_integrity_escalation 673.980s 7867.782us 1 1 100.00
chip_sw_sysrst_ctrl_reset 1 2 50.00
chip_sw_pwrmgr_sysrst_ctrl_reset 1002.270s 9583.104us 1 1 100.00
chip_sw_sysrst_ctrl_reset 994.420s 24164.260us 0 1 0.00
chip_sw_sysrst_ctrl_inputs 1 1 100.00
chip_sw_sysrst_ctrl_inputs 202.400s 3377.180us 1 1 100.00
chip_sw_sysrst_ctrl_outputs 1 1 100.00
chip_sw_sysrst_ctrl_outputs 247.530s 4439.195us 1 1 100.00
chip_sw_sysrst_ctrl_in_irq 1 1 100.00
chip_sw_sysrst_ctrl_in_irq 374.470s 5327.612us 1 1 100.00
chip_sw_sysrst_ctrl_sleep_wakeup 0 1 0.00
chip_sw_sysrst_ctrl_reset 994.420s 24164.260us 0 1 0.00
chip_sw_sysrst_ctrl_sleep_reset 0 1 0.00
chip_sw_sysrst_ctrl_reset 994.420s 24164.260us 0 1 0.00
chip_sw_sysrst_ctrl_ec_rst_l 0 1 0.00
chip_sw_sysrst_ctrl_ec_rst_l 218.520s 5010.340us 0 1 0.00
chip_sw_sysrst_ctrl_flash_wp_l 0 1 0.00
chip_sw_sysrst_ctrl_ec_rst_l 218.520s 5010.340us 0 1 0.00
chip_sw_sysrst_ctrl_ulp_z3_wakeup 1 2 50.00
chip_sw_sysrst_ctrl_ulp_z3_wakeup 330.010s 6792.680us 1 1 100.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 3600.172s 0.000us 0 1 0.00
chip_sw_usbdev_vbus 1 1 100.00
chip_sw_usbdev_vbus 203.180s 3601.906us 1 1 100.00
chip_sw_usbdev_pullup 1 1 100.00
chip_sw_usbdev_pullup 164.480s 3110.744us 1 1 100.00
chip_sw_usbdev_aon_pullup 1 1 100.00
chip_sw_usbdev_aon_pullup 332.160s 4011.734us 1 1 100.00
chip_sw_usbdev_setup_rx 1 1 100.00
chip_sw_usbdev_setuprx 338.700s 4219.509us 1 1 100.00
chip_sw_usbdev_config_host 1 1 100.00
chip_sw_usbdev_config_host 1062.970s 8511.996us 1 1 100.00
chip_sw_usbdev_pincfg 1 1 100.00
chip_sw_usbdev_pincfg 5818.990s 31622.869us 1 1 100.00
chip_sw_usbdev_tx_rx 1 1 100.00
chip_sw_usbdev_dpi 2135.380s 12883.505us 1 1 100.00
chip_sw_usbdev_toggle_restore 1 1 100.00
chip_sw_usbdev_toggle_restore 153.160s 3282.669us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_aes_masking_off 1 1 100.00
chip_sw_aes_masking_off 252.500s 3951.227us 1 1 100.00
chip_sw_rv_core_ibex_lockstep_glitch 0 1 0.00
chip_sw_rv_core_ibex_lockstep_glitch 125.850s 3204.633us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_coremark 1 1 100.00
chip_sw_coremark 11638.190s 68756.517us 1 1 100.00
chip_sw_power_max_load 1 1 100.00
chip_sw_power_virus 1087.000s 7113.284us 1 1 100.00
rom_e2e_debug 0 3 0.00
rom_e2e_jtag_debug_test_unlocked0 552.220s 8122.467us 0 1 0.00
rom_e2e_jtag_debug_dev 184.930s 4214.765us 0 1 0.00
rom_e2e_jtag_debug_rma 576.030s 7537.268us 0 1 0.00
rom_e2e_jtag_inject 0 3 0.00
rom_e2e_jtag_inject_test_unlocked0 77.780s 2600.825us 0 1 0.00
rom_e2e_jtag_inject_dev 134.180s 3723.171us 0 1 0.00
rom_e2e_jtag_inject_rma 115.980s 4053.049us 0 1 0.00
rom_e2e_self_hash 0 1 0.00
rom_e2e_self_hash 111.200s 0.000us 0 1 0.00
chip_sw_clkmgr_jitter_cycle_measurements 0 1 0.00
chip_sw_clkmgr_jitter_frequency 355.150s 4134.400us 0 1 0.00
chip_sw_edn_boot_mode 1 1 100.00
chip_sw_edn_boot_mode 344.120s 3479.299us 1 1 100.00
chip_sw_edn_auto_mode 1 1 100.00
chip_sw_edn_auto_mode 805.260s 5209.189us 1 1 100.00
chip_sw_edn_sw_mode 1 1 100.00
chip_sw_edn_sw_mode 1419.730s 9438.063us 1 1 100.00
chip_sw_edn_kat 1 1 100.00
chip_sw_edn_kat 269.460s 3108.090us 1 1 100.00
chip_sw_flash_memory_protection 1 1 100.00
chip_sw_flash_ctrl_mem_protection 714.660s 5922.344us 1 1 100.00
chip_sw_otp_ctrl_vendor_test_csr_access 1 1 100.00
chip_sw_otp_ctrl_vendor_test_csr_access 73.850s 2395.170us 1 1 100.00
chip_sw_otp_ctrl_escalation 0 1 0.00
chip_sw_otp_ctrl_escalation 192.840s 3889.116us 0 1 0.00
chip_sw_sensor_ctrl_deep_sleep_wake_up 1 1 100.00
chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up 433.300s 7674.917us 1 1 100.00
chip_sw_pwrmgr_usb_clk_disabled_when_active 1 1 100.00
chip_sw_pwrmgr_usb_clk_disabled_when_active 430.520s 6676.501us 1 1 100.00
chip_sw_all_resets 1 1 100.00
chip_sw_pwrmgr_all_reset_reqs 1346.570s 17542.666us 1 1 100.00
chip_rv_dm_perform_debug 0 3 0.00
rom_e2e_jtag_debug_test_unlocked0 552.220s 8122.467us 0 1 0.00
rom_e2e_jtag_debug_dev 184.930s 4214.765us 0 1 0.00
rom_e2e_jtag_debug_rma 576.030s 7537.268us 0 1 0.00
chip_sw_rv_dm_access_after_hw_reset 1 1 100.00
chip_sw_rv_dm_access_after_escalation_reset 434.010s 6019.364us 1 1 100.00
chip_sw_plic_alerts 1 1 100.00
chip_sw_all_escalation_resets 475.910s 6787.579us 1 1 100.00
tick_configuration 1 1 100.00
chip_sw_rv_timer_systick_test 5938.350s 38597.658us 1 1 100.00
counter_wrap 1 1 100.00
chip_sw_rv_timer_systick_test 5938.350s 38597.658us 1 1 100.00
chip_sw_spi_device_output_when_disabled_or_sleeping 1 1 100.00
chip_sw_spi_device_pinmux_sleep_retention 232.760s 4333.944us 1 1 100.00
chip_sw_uart_watermarks 1 1 100.00
chip_sw_uart_tx_rx 410.600s 5020.956us 1 1 100.00
chip_sw_usbdev_stream 1 1 100.00
chip_sw_usbdev_stream 3447.110s 18644.888us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 7 11 63.64
chip_sival_flash_info_access 207.060s 3903.991us 1 1 100.00
chip_sw_rstmgr_rst_cnsty_escalation 22.940s 10.160us 0 1 0.00
chip_sw_otp_ctrl_rot_auth_config 6.150s 0.000us 0 1 0.00
chip_sw_otp_ctrl_ecc_error_vendor_test 170.770s 3431.001us 1 1 100.00
chip_sw_otp_ctrl_descrambling 212.960s 3255.648us 1 1 100.00
chip_sw_pwrmgr_lowpower_cancel 281.520s 4492.251us 1 1 100.00
chip_sw_pwrmgr_sleep_wake_5_bug 9.251s 0.000us 0 1 0.00
chip_sw_flash_ctrl_write_clear 266.880s 3061.473us 1 1 100.00
ate_bootstrap_flash_erase 786.160s 10010.100us 0 1 0.00
ate_bootstrap_one_frame 7141.310s 43863.550us 1 1 100.00
ate_bootstrap_disjoint 10499.430s 80670.432us 1 1 100.00

Error Messages

   Test seed line log context
Error-[NOA] Null object access 7 test runs
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 23472523492466609933848756798106476198320771019043196843166877177894735591128 330
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_debug_test_unlocked0 33378775238468472182751411542192660628001041586285816613827079967386729711578 360
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 903
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_debug_dev 60172027302490032097839257533060066520926056978535071850664713295521893215522 327
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_debug_rma 67386424612326081007299770394640307502753060461477540223861680147324180843958 360
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 903
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_test_unlocked0 90702864029948219082011563703447355830489274239123222412680441453639003557311 311
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_dev 97457653596786769375057308544643739768592949742815810057183866507332347354505 315
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_rma 57518685348838204993579419849873336694368775829960830187513459651157166632780 311
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
Offending '(rstreqs[*] && (reset_cause == HwReq))' 6 test runs
chip_sw_pwrmgr_random_sleep_all_reset_reqs 33338780971555799922076520186371183108723368386755788166687035085556818941446 323
UVM_ERROR @ 6604.620000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 6604.620000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 30837232809086051166647877234387118624755896164690667669738963774525922305666 335
UVM_ERROR @ 11697.409000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 11697.409000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_deep_sleep_por_reset 1921115921918719924164144961980713290635055286213396258159142471620934097377 328
UVM_ERROR @ 8966.834000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 8966.834000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_random_sleep_power_glitch_reset 24685353509138350213828406029928957780657014911606047868117090033351047483209 385
UVM_ERROR @ 25621.480000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 25621.480000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_sysrst_ctrl_reset 49360066613357044892067054634213220523517790731138160605034961765137102714092 337
UVM_ERROR @ 24164.260000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 24164.260000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_aon_timer_wdog_bite_reset 110398367017459632425064246157253519514586969367408442779450648969982083761510 322
UVM_ERROR @ 9041.026000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 9041.026000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [lc_walkthrough_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected 3 test runs
chip_sw_lc_walkthrough_dev 104642151887211031050555450038698734907886803893025681453249795702330871703810 377
UVM_INFO @ 13188.764480 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_walkthrough_prod 17464908091604535820857584068089294525940895007982405590301281464854373929413 377
UVM_INFO @ 12015.018589 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_walkthrough_rma 23326517932986495891483072864589662816209255439777862019234621407151396634066 349
UVM_INFO @ 6031.407080 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes 2 test runs
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 96050567198635465415580887316943433257326640070024965373203577259775367909984 None
chip_sw_alert_handler_lpg_sleep_mode_pings 69553623773768562882873098361882689573591065405343712536796489167413332055060 None
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:322) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns 2 test runs
chip_sw_hmac_multistream 57392164486978756989485552612700648268779034094338497172992962419733559836580 378
UVM_INFO @ 12026.781979 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_keymgr_sideload_otbn 24662406767185371591157836001268861867858335476855412457326529608104484684348 344
UVM_INFO @ 20026.802406 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:615) scoreboard [scoreboard] On interface chip_reg_block, item had unexpected d_error value(predicted *, but saw *). 2 test runs
chip_tl_errors 60025141510086983155544915353686718969741426383965751966222783626893407268450 220
TL item was: req: (cip_tl_seq_item@34211) { a_addr: 'h106d8 a_data: 'h5d500d7e a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h20 a_opcode: 'h4 a_user: 'h1b688 d_param: 'h0 d_source: 'h20 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2231.760308 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_csr_mem_rw_with_rand_reset 40802130828836088563235274992038900193028290411190050899837845490975532644873 232
TL item was: req: (cip_tl_seq_item@32467) { a_addr: 'h105d8 a_data: 'h8107973d a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h1d a_opcode: 'h4 a_user: 'h1bac7 d_param: 'h0 d_source: 'h1d d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 3010.654750 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$'] 2 test runs
chip_sw_pwrmgr_sleep_wake_5_bug 104222316285135565694702813323570908532284004362017189546913886005580940091362 None
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_self_hash 114111240632270169135229974813949080609053953806349680334135335844336060946009 None
Another command (pid=564076) is running. Waiting for it to complete on the server (server_pid=268042)...
Another command (pid=579422) is running. Waiting for it to complete on the server (server_pid=268042)...
Another command (pid=471267) is running. Waiting for it to complete on the server (server_pid=268042)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
UVM_FATAL @ * us: (sec_cm_pkg.sv:48) [sec_cm_pkg::find_sec_cm_if_proxy] no proxy with path *rstmgr.u_d0_spi_host*.leaf_rst_path 1 test run
chip_sw_rstmgr_rst_cnsty_escalation 97990619761126152719045844175860453648816877798112145491547693873664999674054 304
UVM_INFO @ 10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty 1 test run
chip_sw_spi_device_pass_through_collision 22078307270802312561532265953524771534841732735680095372024264413735411151595 330
UVM_INFO @ 4412.777423 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [flash_ctrl_lc_rw_en_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected 1 test run
chip_sw_flash_ctrl_lc_rw_en 22665827719048264989882151425610305319770693811423712956494690163770611272277 312
UVM_INFO @ 3003.860506 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to * 1 test run
chip_sw_otp_ctrl_lc_signals_rma 29662790327136033986249772938959527458135915767944286782101631709440578438453 345
UVM_INFO @ 8495.815496 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))' 1 test run
chip_sw_otp_ctrl_escalation 104878315941928921060642563467084925589558612093684163882136080334434037109146 319
UVM_ERROR @ 3889.116088 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 3889.116088 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[Otp]] file otp_img_test_unlocked0_manuf_empty.*.vmem could not be opened for r mode 1 test run
chip_sw_otp_ctrl_rot_auth_config 56618800276652006340390388068252530244011588043522656250836181685845923418172 290
UVM_INFO @ 0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '((~rst_ni) === (~seed_en_q))' 1 test run
chip_sw_pwrmgr_full_aon_reset 39598796066326888582063241380721758784263832377668258514990251401425164270379 321
UVM_ERROR @ 5281.457547 us: (otbn_rnd.sv:233) [ASSERT FAILED] UrndNoReseedOnReset_A
UVM_INFO @ 5281.457547 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(!$fell((pwrmgr_data_o.done == MuBi4True)))' 1 test run
chip_sw_pwrmgr_sleep_power_glitch_reset 48021127820117313649798951810462077949588279769210411846305341120340068728385 316
UVM_ERROR @ 4038.207780 us: (rom_ctrl.sv:590) [ASSERT FAILED] PwrmgrDataChk_A
UVM_INFO @ 4038.207780 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_sysrst_ctrl_ec_rst_l_vseq.sv:138) [chip_sw_sysrst_ctrl_ec_rst_l_vseq] Timed out waiting for ec_rst to go high. 1 test run
chip_sw_sysrst_ctrl_ec_rst_l 49634919494586944407728685811050922917030250002864625484107766644759716264815 319
UVM_INFO @ 5010.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:351)] CHECK-fail: Expect alert *! 1 test run
chip_sw_alert_test 75470020002393618400416216537981892042778677847985128271985777627471871906779 315
UVM_INFO @ 3409.457212 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0) 1 test run
chip_sw_alert_handler_lpg_sleep_mode_alerts 37316073197073586848860786974045430520198253962112042318916586912206855199788 316
UVM_INFO @ 3062.593025 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [clkmgr_jitter_frequency_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected 1 test run
chip_sw_clkmgr_jitter_frequency 7808518342336863045906624249551677280862263692905719178113098605226453507391 346
UVM_INFO @ 4134.399843 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_rv_dm_access_after_wakeup_vseq.sv:93) [chip_sw_rv_dm_access_after_wakeup_vseq] Timed out waiting for device to wakeup from deep sleep. 1 test run
chip_sw_rv_dm_access_after_wakeup 113880726764608469822719170462730540720669313623815397447246446456350876332231 337
UVM_INFO @ 14202.250232 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_vseq.sv:660) [chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch 1 test run
chip_rv_dm_lc_disabled 65811072476405029097773877782263108322770103351396172137751521873199532344959 259
UVM_INFO @ 11803.813864 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:738) [chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (* [*] vs * [*]) Major alert did not match expectation. 1 test run
chip_sw_rv_core_ibex_lockstep_glitch 6395294817759636413927587925318529350152093011439659618327603237032598477004 325
UVM_INFO @ 3204.632830 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_power_idle_load_vseq.sv:24) [chip_sw_power_idle_load_vseq] timeout waiting for SW sync GPIO (*) 1 test run
chip_sw_power_idle_load 14549239450324856571497619555797524570139456812717262338350286419776677719361 321
UVM_INFO @ 15825.497193 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_power_sleep_load_vseq.sv:47) [chip_sw_power_sleep_load_vseq] timeout waiting for SW sync GPIO (*) 1 test run
chip_sw_power_sleep_load 68170397411974018826899455069855066959325913685679515893436363418357678886984 337
UVM_INFO @ 15183.278714 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/lib/testing/autogen/isr_testutils.c:41)] CHECK-fail: Only adc_ctrl IRQ * expected to fire. Actual IRQ state = * 1 test run
chip_sw_ast_clk_rst_inputs 115311248777570564905298321232374721574730393933062272443613924192865017046444 335
UVM_INFO @ 9889.796909 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (csr_utils_pkg.sv:619) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout chip_reg_block.spi_device.cmd_info_*.opcode (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=1) 1 test run
ate_bootstrap_flash_erase 106301426139678457750361456074652249945999327988452198389945262296613777549929 280
UVM_INFO @ 10010.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rom_e2e_keymgr_init_otp_no_meas_sim_dv(sw/device/silicon_creator/rom/e2e/keymgr/rom_e2e_keymgr_init_test.c:38)] DIF-fail: dif_otp_ctrl_get_digest( &otp_ctrl, kDifOtpCtrlPartitionCreatorSwCfg, &creator_digest) returns * 1 test run
rom_e2e_keymgr_init_rom_ext_no_meas 96802006377758998642649869294978374453365231838481484036525595390321491148787 327
UVM_INFO @ 18370.068376 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rom_e2e_keymgr_init_otp_invalid_meas_sim_dv(sw/device/silicon_creator/rom/e2e/keymgr/rom_e2e_keymgr_init_test.c:38)] DIF-fail: dif_otp_ctrl_get_digest( &otp_ctrl, kDifOtpCtrlPartitionCreatorSwCfg, &creator_digest) returns * 1 test run
rom_e2e_keymgr_init_rom_ext_invalid_meas 68672625578587465166958574421478578804205595652434410099241313359587170882372 327
UVM_INFO @ 16897.641000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_lc_raw_unlock_vseq.sv:57) [chip_sw_lc_raw_unlock_vseq] Timed out waiting for clkmgr to confirm extclk enablement 1 test run
rom_raw_unlock 20346505693608367390507054978686160349605633215759520333123473335782630967732 325
UVM_INFO @ 15597.031494 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '$stable(key_data_i)' 1 test run
rom_keymgr_functest 55041175319481038843271518866184813267823995489014064028389597939137349942334 330
UVM_ERROR @ 6556.504152 us: (kmac_core.sv:464) [ASSERT FAILED] KeyDataStableWhenValid_M
UVM_INFO @ 6556.504152 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---