Simulation Results: clkmgr

 
06/08/2026 15:30:30 DVSim: v1.50.0 sha: 377160a json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 92.36 %
  • code
  • 97.69 %
  • assert
  • 93.79 %
  • func
  • 85.59 %
  • line
  • 98.85 %
  • branch
  • 98.64 %
  • cond
  • 91.78 %
  • toggle
  • 99.19 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
83.33%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
clkmgr_smoke 0.820s 63.055us 1 1 100.00
csr_hw_reset 1 1 100.00
clkmgr_csr_hw_reset 0.720s 50.425us 1 1 100.00
csr_rw 1 1 100.00
clkmgr_csr_rw 1.170s 283.173us 1 1 100.00
csr_bit_bash 1 1 100.00
clkmgr_csr_bit_bash 11.240s 5004.948us 1 1 100.00
csr_aliasing 1 1 100.00
clkmgr_csr_aliasing 1.110s 138.654us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
clkmgr_csr_mem_rw_with_rand_reset 0.890s 33.634us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
clkmgr_csr_rw 1.170s 283.173us 1 1 100.00
clkmgr_csr_aliasing 1.110s 138.654us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 1 1 100.00
clkmgr_peri 0.970s 32.110us 1 1 100.00
trans_enables 1 1 100.00
clkmgr_trans 0.870s 34.432us 1 1 100.00
extclk 1 1 100.00
clkmgr_extclk 0.680s 17.935us 1 1 100.00
clk_status 1 1 100.00
clkmgr_clk_status 0.610s 16.534us 1 1 100.00
jitter 1 1 100.00
clkmgr_smoke 0.820s 63.055us 1 1 100.00
frequency 1 1 100.00
clkmgr_frequency 2.830s 809.376us 1 1 100.00
frequency_timeout 1 1 100.00
clkmgr_frequency_timeout 4.550s 859.793us 1 1 100.00
frequency_overflow 1 1 100.00
clkmgr_frequency 2.830s 809.376us 1 1 100.00
stress_all 1 1 100.00
clkmgr_stress_all 15.660s 5447.256us 1 1 100.00
alert_test 1 1 100.00
clkmgr_alert_test 0.770s 49.251us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
clkmgr_tl_errors 1.650s 71.997us 1 1 100.00
tl_d_illegal_access 1 1 100.00
clkmgr_tl_errors 1.650s 71.997us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
clkmgr_csr_hw_reset 0.720s 50.425us 1 1 100.00
clkmgr_csr_rw 1.170s 283.173us 1 1 100.00
clkmgr_csr_aliasing 1.110s 138.654us 1 1 100.00
clkmgr_same_csr_outstanding 1.040s 122.709us 1 1 100.00
tl_d_partial_access 4 4 100.00
clkmgr_csr_hw_reset 0.720s 50.425us 1 1 100.00
clkmgr_csr_rw 1.170s 283.173us 1 1 100.00
clkmgr_csr_aliasing 1.110s 138.654us 1 1 100.00
clkmgr_same_csr_outstanding 1.040s 122.709us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 1 2 50.00
clkmgr_sec_cm 0.720s 6.164us 0 1 0.00
clkmgr_tl_intg_err 2.010s 477.317us 1 1 100.00
shadow_reg_update_error 0 1 0.00
clkmgr_shadow_reg_errors 759.460s 200000.000us 0 1 0.00
shadow_reg_read_clear_staged_value 0 1 0.00
clkmgr_shadow_reg_errors 759.460s 200000.000us 0 1 0.00
shadow_reg_storage_error 0 1 0.00
clkmgr_shadow_reg_errors 759.460s 200000.000us 0 1 0.00
shadowed_reset_glitch 0 1 0.00
clkmgr_shadow_reg_errors 759.460s 200000.000us 0 1 0.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
clkmgr_shadow_reg_errors_with_csr_rw 1.960s 122.176us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
clkmgr_tl_intg_err 2.010s 477.317us 1 1 100.00
sec_cm_meas_clk_bkgn_chk 1 1 100.00
clkmgr_frequency 2.830s 809.376us 1 1 100.00
sec_cm_timeout_clk_bkgn_chk 1 1 100.00
clkmgr_frequency_timeout 4.550s 859.793us 1 1 100.00
sec_cm_meas_config_shadow 0 1 0.00
clkmgr_shadow_reg_errors 759.460s 200000.000us 0 1 0.00
sec_cm_idle_intersig_mubi 1 1 100.00
clkmgr_idle_intersig_mubi 1.110s 45.700us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
clkmgr_lc_ctrl_intersig_mubi 0.750s 60.427us 1 1 100.00
sec_cm_lc_ctrl_clk_handshake_intersig_mubi 1 1 100.00
clkmgr_lc_clk_byp_req_intersig_mubi 0.930s 52.154us 1 1 100.00
sec_cm_clk_handshake_intersig_mubi 1 1 100.00
clkmgr_clk_handshake_intersig_mubi 1.010s 144.351us 1 1 100.00
sec_cm_div_intersig_mubi 1 1 100.00
clkmgr_div_intersig_mubi 0.790s 44.471us 1 1 100.00
sec_cm_jitter_config_mubi 1 1 100.00
clkmgr_csr_rw 1.170s 283.173us 1 1 100.00
sec_cm_idle_ctr_redun 0 1 0.00
clkmgr_sec_cm 0.720s 6.164us 0 1 0.00
sec_cm_meas_config_regwen 1 1 100.00
clkmgr_csr_rw 1.170s 283.173us 1 1 100.00
sec_cm_clk_ctrl_config_regwen 1 1 100.00
clkmgr_csr_rw 1.170s 283.173us 1 1 100.00
prim_count_check 0 1 0.00
clkmgr_sec_cm 0.720s 6.164us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 1 1 100.00
clkmgr_regwen 1.470s 285.418us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
clkmgr_stress_all_with_rand_reset 68.140s 16308.446us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 1 test run
clkmgr_shadow_reg_errors 3379136924955208596844932810324877401576871707581028683774587377659174357708 75
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1047) virtual_sequencer [clkmgr_common_vseq] Expected alert (fatal_fault) did not fire in * cycles. 1 test run
clkmgr_sec_cm 94145703544548540065132813707434870560621055168170425628765482847068196181208 88
UVM_INFO @ 6163831 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---