Simulation Results: csrng

 
06/08/2026 15:30:30 DVSim: v1.50.0 sha: 377160a json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 89.68 %
  • code
  • 94.79 %
  • assert
  • 94.54 %
  • func
  • 79.72 %
  • block
  • 97.05 %
  • line
  • 97.87 %
  • branch
  • 92.68 %
  • toggle
  • 93.37 %
  • FSM
  • 95.24 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
csrng_smoke 3.000s 27.398us 1 1 100.00
csr_hw_reset 1 1 100.00
csrng_csr_hw_reset 2.000s 39.671us 1 1 100.00
csr_rw 1 1 100.00
csrng_csr_rw 2.000s 15.616us 1 1 100.00
csr_bit_bash 1 1 100.00
csrng_csr_bit_bash 20.000s 1674.228us 1 1 100.00
csr_aliasing 1 1 100.00
csrng_csr_aliasing 4.000s 81.355us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
csrng_csr_mem_rw_with_rand_reset 2.000s 13.959us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
csrng_csr_rw 2.000s 15.616us 1 1 100.00
csrng_csr_aliasing 4.000s 81.355us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
interrupts 1 1 100.00
csrng_intr 5.000s 104.954us 1 1 100.00
alerts 1 1 100.00
csrng_alert 14.000s 909.494us 1 1 100.00
err 1 1 100.00
csrng_err 2.000s 26.315us 1 1 100.00
cmds 1 1 100.00
csrng_cmds 42.000s 3049.272us 1 1 100.00
life cycle 1 1 100.00
csrng_cmds 42.000s 3049.272us 1 1 100.00
stress_all 1 1 100.00
csrng_stress_all 617.000s 15212.518us 1 1 100.00
intr_test 1 1 100.00
csrng_intr_test 1.000s 18.988us 1 1 100.00
alert_test 1 1 100.00
csrng_alert_test 3.000s 106.041us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
csrng_tl_errors 4.000s 195.127us 1 1 100.00
tl_d_illegal_access 1 1 100.00
csrng_tl_errors 4.000s 195.127us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
csrng_csr_hw_reset 2.000s 39.671us 1 1 100.00
csrng_csr_rw 2.000s 15.616us 1 1 100.00
csrng_csr_aliasing 4.000s 81.355us 1 1 100.00
csrng_same_csr_outstanding 2.000s 49.897us 1 1 100.00
tl_d_partial_access 4 4 100.00
csrng_csr_hw_reset 2.000s 39.671us 1 1 100.00
csrng_csr_rw 2.000s 15.616us 1 1 100.00
csrng_csr_aliasing 4.000s 81.355us 1 1 100.00
csrng_same_csr_outstanding 2.000s 49.897us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
csrng_sec_cm 5.000s 351.938us 1 1 100.00
csrng_tl_intg_err 4.000s 366.419us 1 1 100.00
sec_cm_config_regwen 2 2 100.00
csrng_regwen 2.000s 27.362us 1 1 100.00
csrng_csr_rw 2.000s 15.616us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
csrng_alert 14.000s 909.494us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
csrng_stress_all 617.000s 15212.518us 1 1 100.00
sec_cm_main_sm_fsm_sparse 3 3 100.00
csrng_intr 5.000s 104.954us 1 1 100.00
csrng_err 2.000s 26.315us 1 1 100.00
csrng_sec_cm 5.000s 351.938us 1 1 100.00
sec_cm_cmd_stage_fsm_sparse 3 3 100.00
csrng_intr 5.000s 104.954us 1 1 100.00
csrng_err 2.000s 26.315us 1 1 100.00
csrng_sec_cm 5.000s 351.938us 1 1 100.00
sec_cm_ctr_drbg_fsm_sparse 3 3 100.00
csrng_intr 5.000s 104.954us 1 1 100.00
csrng_err 2.000s 26.315us 1 1 100.00
csrng_sec_cm 5.000s 351.938us 1 1 100.00
sec_cm_ctr_drbg_ctr_redun 3 3 100.00
csrng_intr 5.000s 104.954us 1 1 100.00
csrng_err 2.000s 26.315us 1 1 100.00
csrng_sec_cm 5.000s 351.938us 1 1 100.00
sec_cm_gen_cmd_ctr_redun 3 3 100.00
csrng_intr 5.000s 104.954us 1 1 100.00
csrng_err 2.000s 26.315us 1 1 100.00
csrng_sec_cm 5.000s 351.938us 1 1 100.00
sec_cm_ctrl_mubi 1 1 100.00
csrng_alert 14.000s 909.494us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
csrng_intr 5.000s 104.954us 1 1 100.00
csrng_err 2.000s 26.315us 1 1 100.00
sec_cm_constants_lc_gated 1 1 100.00
csrng_stress_all 617.000s 15212.518us 1 1 100.00
sec_cm_sw_genbits_bus_consistency 1 1 100.00
csrng_alert 14.000s 909.494us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
csrng_tl_intg_err 4.000s 366.419us 1 1 100.00
sec_cm_aes_cipher_fsm_sparse 3 3 100.00
csrng_intr 5.000s 104.954us 1 1 100.00
csrng_err 2.000s 26.315us 1 1 100.00
csrng_sec_cm 5.000s 351.938us 1 1 100.00
sec_cm_aes_cipher_fsm_redun 2 2 100.00
csrng_intr 5.000s 104.954us 1 1 100.00
csrng_err 2.000s 26.315us 1 1 100.00
sec_cm_aes_cipher_ctrl_sparse 2 2 100.00
csrng_intr 5.000s 104.954us 1 1 100.00
csrng_err 2.000s 26.315us 1 1 100.00
sec_cm_aes_cipher_fsm_local_esc 2 2 100.00
csrng_intr 5.000s 104.954us 1 1 100.00
csrng_err 2.000s 26.315us 1 1 100.00
sec_cm_aes_cipher_ctr_redun 3 3 100.00
csrng_intr 5.000s 104.954us 1 1 100.00
csrng_err 2.000s 26.315us 1 1 100.00
csrng_sec_cm 5.000s 351.938us 1 1 100.00
sec_cm_aes_cipher_data_reg_local_esc 2 2 100.00
csrng_intr 5.000s 104.954us 1 1 100.00
csrng_err 2.000s 26.315us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
csrng_stress_all_with_rand_reset 3601.000s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
Job timed out after * minutes 1 test run
csrng_stress_all_with_rand_reset 19822561141616660708391093452184197515421291096683389554735530432170862653831 None