Simulation Results: edn/edn0

 
06/08/2026 15:30:30 DVSim: v1.50.0 sha: 377160a json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 88.34 %
  • code
  • 85.22 %
  • assert
  • 98.05 %
  • func
  • 81.75 %
  • line
  • 98.15 %
  • branch
  • 94.00 %
  • cond
  • 89.09 %
  • toggle
  • 91.65 %
  • FSM
  • 53.23 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.810s 49.029us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.880s 16.807us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.830s 15.819us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 1.830s 47.258us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.060s 34.977us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.200s 30.744us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.830s 15.819us 1 1 100.00
edn_csr_aliasing 1.060s 34.977us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.190s 132.625us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.190s 132.625us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.190s 132.625us 1 1 100.00
interrupts 1 1 100.00
edn_intr 0.840s 30.643us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.220s 304.737us 1 1 100.00
errs 1 1 100.00
edn_err 0.900s 25.826us 1 1 100.00
disable 2 2 100.00
edn_disable 0.790s 37.913us 1 1 100.00
edn_disable_auto_req_mode 1.080s 103.531us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 1.670s 183.551us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.770s 21.963us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 0.780s 20.649us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 2.000s 151.988us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 2.000s 151.988us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.880s 16.807us 1 1 100.00
edn_csr_rw 0.830s 15.819us 1 1 100.00
edn_csr_aliasing 1.060s 34.977us 1 1 100.00
edn_same_csr_outstanding 1.000s 104.792us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.880s 16.807us 1 1 100.00
edn_csr_rw 0.830s 15.819us 1 1 100.00
edn_csr_aliasing 1.060s 34.977us 1 1 100.00
edn_same_csr_outstanding 1.000s 104.792us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 6.140s 945.967us 1 1 100.00
edn_tl_intg_err 1.900s 536.846us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.890s 19.712us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.220s 304.737us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 6.140s 945.967us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 6.140s 945.967us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 6.140s 945.967us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 6.140s 945.967us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.220s 304.737us 1 1 100.00
edn_sec_cm 6.140s 945.967us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.220s 304.737us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.900s 536.846us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 79.380s 5053.858us 1 1 100.00