Simulation Results: edn/edn1

 
06/08/2026 15:30:30 DVSim: v1.50.0 sha: 377160a json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 86.83 %
  • code
  • 82.37 %
  • assert
  • 98.70 %
  • func
  • 79.41 %
  • line
  • 97.72 %
  • branch
  • 92.21 %
  • cond
  • 87.23 %
  • toggle
  • 92.62 %
  • FSM
  • 42.05 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.900s 20.172us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.790s 20.967us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.770s 120.096us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 2.460s 144.832us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 0.980s 82.928us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.050s 52.826us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.770s 120.096us 1 1 100.00
edn_csr_aliasing 0.980s 82.928us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.330s 50.572us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.330s 50.572us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.330s 50.572us 1 1 100.00
interrupts 1 1 100.00
edn_intr 0.800s 26.344us 1 1 100.00
alerts 1 1 100.00
edn_alert 0.930s 108.239us 1 1 100.00
errs 1 1 100.00
edn_err 1.250s 21.072us 1 1 100.00
disable 2 2 100.00
edn_disable 0.830s 13.816us 1 1 100.00
edn_disable_auto_req_mode 0.920s 28.323us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 1.170s 55.552us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.800s 24.164us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 0.750s 26.677us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 2.950s 91.392us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 2.950s 91.392us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.790s 20.967us 1 1 100.00
edn_csr_rw 0.770s 120.096us 1 1 100.00
edn_csr_aliasing 0.980s 82.928us 1 1 100.00
edn_same_csr_outstanding 1.050s 134.682us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.790s 20.967us 1 1 100.00
edn_csr_rw 0.770s 120.096us 1 1 100.00
edn_csr_aliasing 0.980s 82.928us 1 1 100.00
edn_same_csr_outstanding 1.050s 134.682us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 4.530s 975.329us 1 1 100.00
edn_tl_intg_err 1.710s 167.623us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.750s 46.466us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 0.930s 108.239us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 4.530s 975.329us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 4.530s 975.329us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 4.530s 975.329us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 4.530s 975.329us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 0.930s 108.239us 1 1 100.00
edn_sec_cm 4.530s 975.329us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 0.930s 108.239us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.710s 167.623us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 18.450s 2645.834us 1 1 100.00