Simulation Results: flash_ctrl

 
06/08/2026 15:30:30 DVSim: v1.50.0 sha: 377160a json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.56 %
  • code
  • 93.75 %
  • assert
  • 97.02 %
  • func
  • 95.91 %
  • line
  • 95.94 %
  • branch
  • 97.16 %
  • cond
  • 93.77 %
  • toggle
  • 96.17 %
  • FSM
  • 85.71 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
flash_ctrl_smoke 23.450s 231.598us 1 1 100.00
smoke_hw 1 1 100.00
flash_ctrl_smoke_hw 15.490s 16.084us 1 1 100.00
csr_hw_reset 1 1 100.00
flash_ctrl_csr_hw_reset 25.770s 26.885us 1 1 100.00
csr_rw 1 1 100.00
flash_ctrl_csr_rw 8.920s 514.814us 1 1 100.00
csr_bit_bash 1 1 100.00
flash_ctrl_csr_bit_bash 58.190s 10560.788us 1 1 100.00
csr_aliasing 1 1 100.00
flash_ctrl_csr_aliasing 22.150s 1503.240us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
flash_ctrl_csr_mem_rw_with_rand_reset 10.140s 55.294us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
flash_ctrl_csr_rw 8.920s 514.814us 1 1 100.00
flash_ctrl_csr_aliasing 22.150s 1503.240us 1 1 100.00
mem_walk 1 1 100.00
flash_ctrl_mem_walk 7.530s 18.222us 1 1 100.00
mem_partial_access 1 1 100.00
flash_ctrl_mem_partial_access 7.050s 35.429us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sw_op 1 1 100.00
flash_ctrl_sw_op 10.380s 29.557us 1 1 100.00
host_read_direct 1 1 100.00
flash_ctrl_host_dir_rd 27.520s 114.217us 1 1 100.00
rma_hw_if 3 3 100.00
flash_ctrl_hw_rma 1223.240s 153205.522us 1 1 100.00
flash_ctrl_hw_rma_reset 517.860s 160191.466us 1 1 100.00
flash_ctrl_lcmgr_intg 10.830s 79.754us 1 1 100.00
host_controller_arb 1 1 100.00
flash_ctrl_host_ctrl_arb 1160.180s 585192.732us 1 1 100.00
erase_suspend 1 1 100.00
flash_ctrl_erase_suspend 224.950s 6995.720us 1 1 100.00
program_reset 1 1 100.00
flash_ctrl_prog_reset 121.370s 2985.556us 1 1 100.00
full_memory_access 1 1 100.00
flash_ctrl_full_mem_access 1655.940s 290360.309us 1 1 100.00
rd_buff_eviction 1 1 100.00
flash_ctrl_rd_buff_evict 57.590s 5725.479us 1 1 100.00
rd_buff_eviction_w_ecc 3 3 100.00
flash_ctrl_rw_evict 15.470s 32.742us 1 1 100.00
flash_ctrl_rw_evict_all_en 19.880s 206.240us 1 1 100.00
flash_ctrl_re_evict 14.960s 696.615us 1 1 100.00
host_arb 1 1 100.00
flash_ctrl_phy_arb 101.560s 704.615us 1 1 100.00
host_interleave 1 1 100.00
flash_ctrl_phy_arb 101.560s 704.615us 1 1 100.00
memory_protection 1 1 100.00
flash_ctrl_mp_regions 120.440s 49470.634us 1 1 100.00
fetch_code 1 1 100.00
flash_ctrl_fetch_code 14.190s 953.626us 1 1 100.00
all_partitions 1 1 100.00
flash_ctrl_rand_ops 108.160s 212.710us 1 1 100.00
error_mp 1 1 100.00
flash_ctrl_error_mp 410.710s 12109.745us 1 1 100.00
error_prog_win 1 1 100.00
flash_ctrl_error_prog_win 355.480s 411.737us 1 1 100.00
error_prog_type 1 1 100.00
flash_ctrl_error_prog_type 821.780s 2063.018us 1 1 100.00
error_read_seed 1 1 100.00
flash_ctrl_hw_read_seed_err 6.120s 23.901us 1 1 100.00
read_write_overflow 1 1 100.00
flash_ctrl_oversize_error 140.470s 1591.443us 1 1 100.00
flash_ctrl_disable 1 1 100.00
flash_ctrl_disable 10.290s 25.625us 1 1 100.00
flash_ctrl_connect 1 1 100.00
flash_ctrl_connect 8.040s 28.328us 1 1 100.00
stress_all 1 1 100.00
flash_ctrl_stress_all 592.020s 1018.995us 1 1 100.00
secret_partition 2 2 100.00
flash_ctrl_hw_sec_otp 72.000s 8024.572us 1 1 100.00
flash_ctrl_otp_reset 63.210s 259.526us 1 1 100.00
isolation_partition 1 1 100.00
flash_ctrl_hw_rma 1223.240s 153205.522us 1 1 100.00
interrupts 4 4 100.00
flash_ctrl_intr_rd 102.830s 5627.515us 1 1 100.00
flash_ctrl_intr_wr 66.140s 11330.636us 1 1 100.00
flash_ctrl_intr_rd_slow_flash 175.800s 24258.617us 1 1 100.00
flash_ctrl_intr_wr_slow_flash 114.970s 44995.649us 1 1 100.00
invalid_op 1 1 100.00
flash_ctrl_invalid_op 64.870s 45848.391us 1 1 100.00
mid_op_rst 1 1 100.00
flash_ctrl_mid_op_rst 48.070s 2603.576us 1 1 100.00
double_bit_err 5 5 100.00
flash_ctrl_read_word_sweep_derr 16.130s 31.239us 1 1 100.00
flash_ctrl_ro_derr 98.590s 3750.086us 1 1 100.00
flash_ctrl_rw_derr 161.880s 2566.569us 1 1 100.00
flash_ctrl_derr_detect 109.690s 14482.955us 1 1 100.00
flash_ctrl_integrity 318.440s 7867.916us 1 1 100.00
single_bit_err 3 3 100.00
flash_ctrl_read_word_sweep_serr 12.550s 81.869us 1 1 100.00
flash_ctrl_ro_serr 82.090s 3129.523us 1 1 100.00
flash_ctrl_rw_serr 138.950s 2142.103us 1 1 100.00
singlebit_err_counter 1 1 100.00
flash_ctrl_serr_counter 45.160s 7273.267us 1 1 100.00
singlebit_err_address 1 1 100.00
flash_ctrl_serr_address 59.270s 6015.998us 1 1 100.00
scramble 5 5 100.00
flash_ctrl_wo 83.710s 2580.663us 1 1 100.00
flash_ctrl_write_word_sweep 7.920s 80.094us 1 1 100.00
flash_ctrl_read_word_sweep 7.910s 105.105us 1 1 100.00
flash_ctrl_ro 87.300s 1666.509us 1 1 100.00
flash_ctrl_rw 322.620s 8510.419us 1 1 100.00
filesystem_support 1 1 100.00
flash_ctrl_fs_sup 20.800s 379.675us 1 1 100.00
rma_write_process_error 2 2 100.00
flash_ctrl_rma_err 539.000s 161147.793us 1 1 100.00
flash_ctrl_hw_prog_rma_wipe_err 81.040s 10019.897us 1 1 100.00
alert_test 1 1 100.00
flash_ctrl_alert_test 6.150s 105.193us 1 1 100.00
intr_test 1 1 100.00
flash_ctrl_intr_test 12.120s 28.416us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
flash_ctrl_tl_errors 9.100s 89.653us 1 1 100.00
tl_d_illegal_access 1 1 100.00
flash_ctrl_tl_errors 9.100s 89.653us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
flash_ctrl_csr_hw_reset 25.770s 26.885us 1 1 100.00
flash_ctrl_csr_rw 8.920s 514.814us 1 1 100.00
flash_ctrl_csr_aliasing 22.150s 1503.240us 1 1 100.00
flash_ctrl_same_csr_outstanding 8.270s 108.404us 1 1 100.00
tl_d_partial_access 4 4 100.00
flash_ctrl_csr_hw_reset 25.770s 26.885us 1 1 100.00
flash_ctrl_csr_rw 8.920s 514.814us 1 1 100.00
flash_ctrl_csr_aliasing 22.150s 1503.240us 1 1 100.00
flash_ctrl_same_csr_outstanding 8.270s 108.404us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
flash_ctrl_shadow_reg_errors 21.590s 266.411us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
flash_ctrl_shadow_reg_errors 21.590s 266.411us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
flash_ctrl_shadow_reg_errors 21.590s 266.411us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
flash_ctrl_shadow_reg_errors 21.590s 266.411us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
flash_ctrl_shadow_reg_errors_with_csr_rw 18.500s 185.736us 1 1 100.00
tl_intg_err 2 2 100.00
flash_ctrl_sec_cm 1703.790s 1196.879us 1 1 100.00
flash_ctrl_tl_intg_err 310.830s 1716.815us 1 1 100.00
sec_cm_reg_bus_integrity 1 1 100.00
flash_ctrl_tl_intg_err 310.830s 1716.815us 1 1 100.00
sec_cm_host_bus_integrity 1 1 100.00
flash_ctrl_tl_intg_err 310.830s 1716.815us 1 1 100.00
sec_cm_mem_bus_integrity 2 2 100.00
flash_ctrl_rd_intg 18.660s 942.553us 1 1 100.00
flash_ctrl_wr_intg 6.840s 179.309us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
flash_ctrl_smoke 23.450s 231.598us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 4 4 100.00
flash_ctrl_otp_reset 63.210s 259.526us 1 1 100.00
flash_ctrl_disable 10.290s 25.625us 1 1 100.00
flash_ctrl_sec_info_access 45.290s 7379.816us 1 1 100.00
flash_ctrl_connect 8.040s 28.328us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
flash_ctrl_config_regwen 6.450s 42.353us 1 1 100.00
sec_cm_data_regions_config_regwen 1 1 100.00
flash_ctrl_csr_rw 8.920s 514.814us 1 1 100.00
sec_cm_data_regions_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 21.590s 266.411us 1 1 100.00
sec_cm_info_regions_config_regwen 1 1 100.00
flash_ctrl_csr_rw 8.920s 514.814us 1 1 100.00
sec_cm_info_regions_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 21.590s 266.411us 1 1 100.00
sec_cm_bank_config_regwen 1 1 100.00
flash_ctrl_csr_rw 8.920s 514.814us 1 1 100.00
sec_cm_bank_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 21.590s 266.411us 1 1 100.00
sec_cm_mem_ctrl_global_esc 1 1 100.00
flash_ctrl_disable 10.290s 25.625us 1 1 100.00
sec_cm_mem_ctrl_local_esc 2 2 100.00
flash_ctrl_rd_intg 18.660s 942.553us 1 1 100.00
flash_ctrl_access_after_disable 6.380s 79.736us 1 1 100.00
sec_cm_mem_addr_infection 1 1 100.00
flash_ctrl_host_addr_infection 16.970s 28.412us 1 1 100.00
sec_cm_mem_disable_config_mubi 1 1 100.00
flash_ctrl_disable 10.290s 25.625us 1 1 100.00
sec_cm_exec_config_redun 1 1 100.00
flash_ctrl_fetch_code 14.190s 953.626us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
flash_ctrl_rw 322.620s 8510.419us 1 1 100.00
sec_cm_mem_integrity 3 3 100.00
flash_ctrl_rw_serr 138.950s 2142.103us 1 1 100.00
flash_ctrl_rw_derr 161.880s 2566.569us 1 1 100.00
flash_ctrl_integrity 318.440s 7867.916us 1 1 100.00
sec_cm_rma_entry_mem_sec_wipe 1 1 100.00
flash_ctrl_hw_rma 1223.240s 153205.522us 1 1 100.00
sec_cm_ctrl_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1703.790s 1196.879us 1 1 100.00
sec_cm_phy_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1703.790s 1196.879us 1 1 100.00
sec_cm_phy_prog_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1703.790s 1196.879us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
flash_ctrl_sec_cm 1703.790s 1196.879us 1 1 100.00
sec_cm_phy_arbiter_ctrl_redun 1 1 100.00
flash_ctrl_phy_arb_redun 10.190s 843.895us 1 1 100.00
sec_cm_phy_host_grant_ctrl_consistency 1 1 100.00
flash_ctrl_phy_host_grant_err 6.790s 85.339us 1 1 100.00
sec_cm_phy_ack_ctrl_consistency 1 1 100.00
flash_ctrl_phy_ack_consistency 6.410s 50.166us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
flash_ctrl_sec_cm 1703.790s 1196.879us 1 1 100.00
sec_cm_mem_tl_lc_gate_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1703.790s 1196.879us 1 1 100.00
sec_cm_prog_tl_lc_gate_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1703.790s 1196.879us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
asymmetric_read_path 1 1 100.00
flash_ctrl_rd_ooo 23.600s 94.035us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
flash_ctrl_basic_rw 227.860s 6313.164us 1 1 100.00