Simulation Results: hmac

 
06/08/2026 15:30:30 DVSim: v1.50.0 sha: 377160a json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 79.04 %
  • code
  • 97.70 %
  • assert
  • 97.60 %
  • func
  • 41.81 %
  • line
  • 99.64 %
  • branch
  • 98.84 %
  • cond
  • 95.90 %
  • toggle
  • 100.00 %
  • FSM
  • 94.12 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
hmac_smoke 3.280s 910.994us 1 1 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 0.730s 93.818us 1 1 100.00
csr_rw 1 1 100.00
hmac_csr_rw 0.800s 344.387us 1 1 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 4.310s 167.914us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 2.180s 313.048us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 521.720s 62242.368us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
hmac_csr_rw 0.800s 344.387us 1 1 100.00
hmac_csr_aliasing 2.180s 313.048us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 1 1 100.00
hmac_long_msg 17.810s 39557.856us 1 1 100.00
back_pressure 1 1 100.00
hmac_back_pressure 65.470s 20851.920us 1 1 100.00
test_vectors 6 6 100.00
hmac_test_sha256_vectors 8.570s 922.409us 1 1 100.00
hmac_test_sha384_vectors 421.600s 19378.041us 1 1 100.00
hmac_test_sha512_vectors 378.940s 16809.961us 1 1 100.00
hmac_test_hmac256_vectors 8.000s 394.210us 1 1 100.00
hmac_test_hmac384_vectors 9.720s 1675.131us 1 1 100.00
hmac_test_hmac512_vectors 11.670s 926.368us 1 1 100.00
burst_wr 1 1 100.00
hmac_burst_wr 1.630s 590.331us 1 1 100.00
datapath_stress 1 1 100.00
hmac_datapath_stress 66.700s 2834.282us 1 1 100.00
error 1 1 100.00
hmac_error 5.340s 1016.166us 1 1 100.00
wipe_secret 1 1 100.00
hmac_wipe_secret 17.810s 1805.774us 1 1 100.00
save_and_restore 6 6 100.00
hmac_smoke 3.280s 910.994us 1 1 100.00
hmac_long_msg 17.810s 39557.856us 1 1 100.00
hmac_back_pressure 65.470s 20851.920us 1 1 100.00
hmac_datapath_stress 66.700s 2834.282us 1 1 100.00
hmac_burst_wr 1.630s 590.331us 1 1 100.00
hmac_stress_all 274.540s 34057.889us 1 1 100.00
fifo_empty_status_interrupt 11 11 100.00
hmac_smoke 3.280s 910.994us 1 1 100.00
hmac_long_msg 17.810s 39557.856us 1 1 100.00
hmac_back_pressure 65.470s 20851.920us 1 1 100.00
hmac_datapath_stress 66.700s 2834.282us 1 1 100.00
hmac_wipe_secret 17.810s 1805.774us 1 1 100.00
hmac_test_sha256_vectors 8.570s 922.409us 1 1 100.00
hmac_test_sha384_vectors 421.600s 19378.041us 1 1 100.00
hmac_test_sha512_vectors 378.940s 16809.961us 1 1 100.00
hmac_test_hmac256_vectors 8.000s 394.210us 1 1 100.00
hmac_test_hmac384_vectors 9.720s 1675.131us 1 1 100.00
hmac_test_hmac512_vectors 11.670s 926.368us 1 1 100.00
wide_digest_configurable_key_length 14 14 100.00
hmac_smoke 3.280s 910.994us 1 1 100.00
hmac_long_msg 17.810s 39557.856us 1 1 100.00
hmac_back_pressure 65.470s 20851.920us 1 1 100.00
hmac_datapath_stress 66.700s 2834.282us 1 1 100.00
hmac_burst_wr 1.630s 590.331us 1 1 100.00
hmac_error 5.340s 1016.166us 1 1 100.00
hmac_wipe_secret 17.810s 1805.774us 1 1 100.00
hmac_test_sha256_vectors 8.570s 922.409us 1 1 100.00
hmac_test_sha384_vectors 421.600s 19378.041us 1 1 100.00
hmac_test_sha512_vectors 378.940s 16809.961us 1 1 100.00
hmac_test_hmac256_vectors 8.000s 394.210us 1 1 100.00
hmac_test_hmac384_vectors 9.720s 1675.131us 1 1 100.00
hmac_test_hmac512_vectors 11.670s 926.368us 1 1 100.00
hmac_stress_all 274.540s 34057.889us 1 1 100.00
stress_all 1 1 100.00
hmac_stress_all 274.540s 34057.889us 1 1 100.00
alert_test 1 1 100.00
hmac_alert_test 0.610s 17.612us 1 1 100.00
intr_test 1 1 100.00
hmac_intr_test 0.690s 17.880us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
hmac_tl_errors 1.200s 94.139us 1 1 100.00
tl_d_illegal_access 1 1 100.00
hmac_tl_errors 1.200s 94.139us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
hmac_csr_hw_reset 0.730s 93.818us 1 1 100.00
hmac_csr_rw 0.800s 344.387us 1 1 100.00
hmac_csr_aliasing 2.180s 313.048us 1 1 100.00
hmac_same_csr_outstanding 1.390s 34.576us 1 1 100.00
tl_d_partial_access 4 4 100.00
hmac_csr_hw_reset 0.730s 93.818us 1 1 100.00
hmac_csr_rw 0.800s 344.387us 1 1 100.00
hmac_csr_aliasing 2.180s 313.048us 1 1 100.00
hmac_same_csr_outstanding 1.390s 34.576us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
hmac_sec_cm 0.870s 73.164us 1 1 100.00
hmac_tl_intg_err 3.370s 489.259us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
hmac_tl_intg_err 3.370s 489.259us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 1 1 100.00
hmac_smoke 3.280s 910.994us 1 1 100.00
stress_reset 1 1 100.00
hmac_stress_reset 1.480s 226.909us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
hmac_stress_all_with_rand_reset 92.390s 31160.809us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 1.750s 98.469us 1 1 100.00