Simulation Results

Simulation Results: i2c

06/08/2026 15:30:30 DVSim: v1.50.0 sha: 377160a json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
84.87 %

code
78.39 %

assert
97.25 %

func
78.96 %

line
96.41 %

branch
92.41 %

cond
85.23 %

toggle
73.87 %

FSM
44.05 %

Validation stages

V1		100.00%
V2		87.80%
V2S		100.00%
V3		0.00%

7/7 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_smoke				1	1	100.00
	i2c_host_smoke	30.750s	1288.910us	1	1	100.00
target_smoke				1	1	100.00
	i2c_target_smoke	7.710s	1786.278us	1	1	100.00
csr_hw_reset				1	1	100.00
	i2c_csr_hw_reset	0.790s	58.853us	1	1	100.00
csr_rw				1	1	100.00
	i2c_csr_rw	0.910s	35.418us	1	1	100.00
csr_bit_bash				1	1	100.00
	i2c_csr_bit_bash	2.050s	321.765us	1	1	100.00
csr_aliasing				1	1	100.00
	i2c_csr_aliasing	1.720s	662.028us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	i2c_csr_mem_rw_with_rand_reset	0.720s	79.980us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	i2c_csr_rw	0.910s	35.418us	1	1	100.00
	i2c_csr_aliasing	1.720s	662.028us	1	1	100.00

36/41 passed

87.80 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_error_intr				0	1	0.00
	i2c_host_error_intr	0.780s	54.664us	0	1	0.00
host_stress_all				0	1	0.00
	i2c_host_stress_all	1.180s	286.222us	0	1	0.00
host_maxperf				1	1	100.00
	i2c_host_perf	6.150s	673.020us	1	1	100.00
host_override				1	1	100.00
	i2c_host_override	0.770s	28.518us	1	1	100.00
host_fifo_watermark				1	1	100.00
	i2c_host_fifo_watermark	66.280s	20655.496us	1	1	100.00
host_fifo_overflow				1	1	100.00
	i2c_host_fifo_overflow	22.070s	1495.485us	1	1	100.00
host_fifo_reset				3	3	100.00
	i2c_host_fifo_reset_fmt	0.920s	153.490us	1	1	100.00
	i2c_host_fifo_fmt_empty	3.460s	538.355us	1	1	100.00
	i2c_host_fifo_reset_rx	6.550s	446.737us	1	1	100.00
host_fifo_full				1	1	100.00
	i2c_host_fifo_full	34.560s	23546.196us	1	1	100.00
host_timeout				1	1	100.00
	i2c_host_stretch_timeout	9.430s	3297.058us	1	1	100.00
i2c_host_mode_toggle				0	1	0.00
	i2c_host_mode_toggle	1.590s	147.308us	0	1	0.00
target_glitch				0	1	0.00
	i2c_target_glitch	1.870s	1028.996us	0	1	0.00
target_stress_all				1	1	100.00
	i2c_target_stress_all	35.470s	81422.328us	1	1	100.00
target_maxperf				1	1	100.00
	i2c_target_perf	3.930s	1707.730us	1	1	100.00
target_fifo_empty				2	2	100.00
	i2c_target_stress_rd	41.680s	2952.913us	1	1	100.00
	i2c_target_intr_smoke	4.480s	2524.248us	1	1	100.00
target_fifo_reset				2	2	100.00
	i2c_target_fifo_reset_acq	0.820s	385.676us	1	1	100.00
	i2c_target_fifo_reset_tx	1.070s	653.922us	1	1	100.00
target_fifo_full				3	3	100.00
	i2c_target_stress_wr	341.080s	41633.532us	1	1	100.00
	i2c_target_stress_rd	41.680s	2952.913us	1	1	100.00
	i2c_target_intr_stress_wr	4.320s	3235.935us	1	1	100.00
target_timeout				1	1	100.00
	i2c_target_timeout	4.420s	2715.545us	1	1	100.00
target_clock_stretch				1	1	100.00
	i2c_target_stretch	2.890s	3542.777us	1	1	100.00
bad_address				1	1	100.00
	i2c_target_bad_addr	2.670s	2901.328us	1	1	100.00
target_mode_glitch				0	1	0.00
	i2c_target_hrst	17.340s	10016.563us	0	1	0.00
target_fifo_watermark				2	2	100.00
	i2c_target_fifo_watermarks_acq	2.210s	2647.938us	1	1	100.00
	i2c_target_fifo_watermarks_tx	0.990s	183.937us	1	1	100.00
host_mode_config_perf				2	2	100.00
	i2c_host_perf	6.150s	673.020us	1	1	100.00
	i2c_host_perf_precise	37.410s	23533.214us	1	1	100.00
host_mode_clock_stretching				1	1	100.00
	i2c_host_stretch_timeout	9.430s	3297.058us	1	1	100.00
target_mode_tx_stretch_ctrl				1	1	100.00
	i2c_target_tx_stretch_ctrl	4.320s	425.077us	1	1	100.00
target_mode_nack_generation				3	3	100.00
	i2c_target_nack_acqfull	1.960s	607.733us	1	1	100.00
	i2c_target_nack_acqfull_addr	1.710s	458.285us	1	1	100.00
	i2c_target_nack_txstretch	1.060s	539.422us	1	1	100.00
host_mode_halt_on_nak				1	1	100.00
	i2c_host_may_nack	4.790s	600.189us	1	1	100.00
target_mode_smbus_maxlen				1	1	100.00
	i2c_target_smbus_maxlen	1.930s	1005.608us	1	1	100.00
alert_test				1	1	100.00
	i2c_alert_test	0.710s	16.871us	1	1	100.00
intr_test				1	1	100.00
	i2c_intr_test	0.860s	15.636us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	i2c_tl_errors	2.080s	503.590us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	i2c_tl_errors	2.080s	503.590us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	i2c_csr_hw_reset	0.790s	58.853us	1	1	100.00
	i2c_csr_rw	0.910s	35.418us	1	1	100.00
	i2c_csr_aliasing	1.720s	662.028us	1	1	100.00
	i2c_same_csr_outstanding	1.000s	57.318us	1	1	100.00
tl_d_partial_access				4	4	100.00
	i2c_csr_hw_reset	0.790s	58.853us	1	1	100.00
	i2c_csr_rw	0.910s	35.418us	1	1	100.00
	i2c_csr_aliasing	1.720s	662.028us	1	1	100.00
	i2c_same_csr_outstanding	1.000s	57.318us	1	1	100.00

V2S

2/2 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	i2c_tl_intg_err	1.920s	140.636us	1	1	100.00
	i2c_sec_cm	0.800s	45.381us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	i2c_tl_intg_err	1.920s	140.636us	1	1	100.00

0/3 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Total
host_stress_all_with_rand_reset				1
	i2c_host_stress_all_with_rand_reset	4.420s	763.306us	1
target_error_intr				1
	i2c_target_unexp_stop	1.020s	226.961us	1
target_stress_all_with_rand_reset				1
	i2c_target_stress_all_with_rand_reset	11.310s	8297.419us	1

Error Messages

	Test	seed	line	log context
UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between				2 test runs
	i2c_host_error_intr	84366172337912803920738636834420574071968729502593749947034116073704606119172	88	UVM_INFO @ 54663732 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	i2c_host_stress_all	84407652803161719729669170846272031628778971342692650768034003809146843859564	118	UVM_INFO @ 286222379 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1286) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.				2 test runs
	i2c_host_stress_all_with_rand_reset	30791456623208643973773858871434051848704227762202700751385991860333739940744	108	UVM_INFO @ 763306246 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	i2c_target_stress_all_with_rand_reset	35744677842382742325165913694699173468239725248102280673851480874373752500865	89	UVM_INFO @ 8297418796 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between				1 test run
	i2c_target_glitch	22926660886627053925760090813581642054881245084687518880089794089359081895570	84	UVM_INFO @ 1028995884 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [] vs [*])				1 test run
	i2c_target_unexp_stop	15811793025436867990326860792753910442250036256338885251564995498584216312557	78	UVM_INFO @ 226960506 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!				1 test run
	i2c_target_hrst	93673351110685649697877894583391484155918471411083554219276955269666743153209	79	UVM_INFO @ 10016563176 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared:				1 test run
	i2c_host_mode_toggle	5758252731651399705612418591999084583704134033741409992317831638313977474016	85	---------------------------------------------------- Name Type Size Value ---------------------------------------------------- mon_dut_item i2c_item - @24927