Simulation Results: keymgr

 
06/08/2026 15:30:30 DVSim: v1.50.0 sha: 377160a json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 87.34 %
  • code
  • 95.20 %
  • assert
  • 97.49 %
  • func
  • 69.32 %
  • line
  • 98.84 %
  • branch
  • 98.08 %
  • cond
  • 93.28 %
  • toggle
  • 95.08 %
  • FSM
  • 90.70 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
keymgr_smoke 1.890s 118.208us 1 1 100.00
random 1 1 100.00
keymgr_random 3.690s 164.459us 1 1 100.00
csr_hw_reset 1 1 100.00
keymgr_csr_hw_reset 0.960s 36.082us 1 1 100.00
csr_rw 1 1 100.00
keymgr_csr_rw 0.910s 139.108us 1 1 100.00
csr_bit_bash 1 1 100.00
keymgr_csr_bit_bash 12.460s 4772.050us 1 1 100.00
csr_aliasing 1 1 100.00
keymgr_csr_aliasing 6.790s 425.641us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
keymgr_csr_mem_rw_with_rand_reset 1.280s 80.130us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
keymgr_csr_rw 0.910s 139.108us 1 1 100.00
keymgr_csr_aliasing 6.790s 425.641us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
cfgen_during_op 1 1 100.00
keymgr_cfg_regwen 2.780s 129.705us 1 1 100.00
sideload 4 4 100.00
keymgr_sideload 2.590s 463.399us 1 1 100.00
keymgr_sideload_kmac 2.090s 409.725us 1 1 100.00
keymgr_sideload_aes 1.920s 99.006us 1 1 100.00
keymgr_sideload_otbn 1.910s 159.294us 1 1 100.00
direct_to_disabled_state 1 1 100.00
keymgr_direct_to_disabled 1.320s 109.404us 1 1 100.00
lc_disable 1 1 100.00
keymgr_lc_disable 2.010s 271.906us 1 1 100.00
kmac_error_response 1 1 100.00
keymgr_kmac_rsp_err 2.880s 231.840us 1 1 100.00
invalid_sw_input 1 1 100.00
keymgr_sw_invalid_input 3.220s 415.598us 1 1 100.00
invalid_hw_input 1 1 100.00
keymgr_hwsw_invalid_input 2.670s 2332.416us 1 1 100.00
sync_async_fault_cross 1 1 100.00
keymgr_sync_async_fault_cross 1.410s 192.025us 1 1 100.00
stress_all 1 1 100.00
keymgr_stress_all 24.970s 3558.155us 1 1 100.00
intr_test 1 1 100.00
keymgr_intr_test 0.690s 12.305us 1 1 100.00
alert_test 1 1 100.00
keymgr_alert_test 0.710s 17.045us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
keymgr_tl_errors 1.400s 355.227us 1 1 100.00
tl_d_illegal_access 1 1 100.00
keymgr_tl_errors 1.400s 355.227us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
keymgr_csr_hw_reset 0.960s 36.082us 1 1 100.00
keymgr_csr_rw 0.910s 139.108us 1 1 100.00
keymgr_csr_aliasing 6.790s 425.641us 1 1 100.00
keymgr_same_csr_outstanding 1.450s 70.432us 1 1 100.00
tl_d_partial_access 4 4 100.00
keymgr_csr_hw_reset 0.960s 36.082us 1 1 100.00
keymgr_csr_rw 0.910s 139.108us 1 1 100.00
keymgr_csr_aliasing 6.790s 425.641us 1 1 100.00
keymgr_same_csr_outstanding 1.450s 70.432us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 1 1 100.00
keymgr_sec_cm 9.450s 2475.405us 1 1 100.00
tl_intg_err 2 2 100.00
keymgr_sec_cm 9.450s 2475.405us 1 1 100.00
keymgr_tl_intg_err 4.950s 271.649us 1 1 100.00
shadow_reg_update_error 1 1 100.00
keymgr_shadow_reg_errors 1.900s 281.556us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
keymgr_shadow_reg_errors 1.900s 281.556us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
keymgr_shadow_reg_errors 1.900s 281.556us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
keymgr_shadow_reg_errors 1.900s 281.556us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
keymgr_shadow_reg_errors_with_csr_rw 8.860s 1033.520us 1 1 100.00
prim_count_check 1 1 100.00
keymgr_sec_cm 9.450s 2475.405us 1 1 100.00
prim_fsm_check 1 1 100.00
keymgr_sec_cm 9.450s 2475.405us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
keymgr_tl_intg_err 4.950s 271.649us 1 1 100.00
sec_cm_config_shadow 1 1 100.00
keymgr_shadow_reg_errors 1.900s 281.556us 1 1 100.00
sec_cm_op_config_regwen 1 1 100.00
keymgr_cfg_regwen 2.780s 129.705us 1 1 100.00
sec_cm_reseed_config_regwen 2 2 100.00
keymgr_random 3.690s 164.459us 1 1 100.00
keymgr_csr_rw 0.910s 139.108us 1 1 100.00
sec_cm_sw_binding_config_regwen 2 2 100.00
keymgr_random 3.690s 164.459us 1 1 100.00
keymgr_csr_rw 0.910s 139.108us 1 1 100.00
sec_cm_max_key_ver_config_regwen 2 2 100.00
keymgr_random 3.690s 164.459us 1 1 100.00
keymgr_csr_rw 0.910s 139.108us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
keymgr_lc_disable 2.010s 271.906us 1 1 100.00
sec_cm_constants_consistency 1 1 100.00
keymgr_hwsw_invalid_input 2.670s 2332.416us 1 1 100.00
sec_cm_intersig_consistency 1 1 100.00
keymgr_hwsw_invalid_input 2.670s 2332.416us 1 1 100.00
sec_cm_hw_key_sw_noaccess 1 1 100.00
keymgr_random 3.690s 164.459us 1 1 100.00
sec_cm_output_keys_ctrl_redun 1 1 100.00
keymgr_sideload_protect 1.650s 1189.897us 1 1 100.00
sec_cm_ctrl_fsm_sparse 1 1 100.00
keymgr_sec_cm 9.450s 2475.405us 1 1 100.00
sec_cm_data_fsm_sparse 1 1 100.00
keymgr_sec_cm 9.450s 2475.405us 1 1 100.00
sec_cm_ctrl_fsm_local_esc 1 1 100.00
keymgr_sec_cm 9.450s 2475.405us 1 1 100.00
sec_cm_ctrl_fsm_consistency 1 1 100.00
keymgr_custom_cm 1.770s 119.969us 1 1 100.00
sec_cm_ctrl_fsm_global_esc 1 1 100.00
keymgr_lc_disable 2.010s 271.906us 1 1 100.00
sec_cm_ctrl_ctr_redun 1 1 100.00
keymgr_sec_cm 9.450s 2475.405us 1 1 100.00
sec_cm_kmac_if_fsm_sparse 1 1 100.00
keymgr_sec_cm 9.450s 2475.405us 1 1 100.00
sec_cm_kmac_if_ctr_redun 1 1 100.00
keymgr_sec_cm 9.450s 2475.405us 1 1 100.00
sec_cm_kmac_if_cmd_ctrl_consistency 1 1 100.00
keymgr_custom_cm 1.770s 119.969us 1 1 100.00
sec_cm_kmac_if_done_ctrl_consistency 1 1 100.00
keymgr_custom_cm 1.770s 119.969us 1 1 100.00
sec_cm_reseed_ctr_redun 1 1 100.00
keymgr_sec_cm 9.450s 2475.405us 1 1 100.00
sec_cm_side_load_sel_ctrl_consistency 1 1 100.00
keymgr_custom_cm 1.770s 119.969us 1 1 100.00
sec_cm_sideload_ctrl_fsm_sparse 1 1 100.00
keymgr_sec_cm 9.450s 2475.405us 1 1 100.00
sec_cm_ctrl_key_integrity 1 1 100.00
keymgr_custom_cm 1.770s 119.969us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
keymgr_stress_all_with_rand_reset 5.410s 2316.114us 1 1 100.00