Simulation Results: lc_ctrl/volatile_unlock_disabled

 
06/08/2026 15:30:30 DVSim: v1.50.0 sha: 377160a json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 90.30 %
  • code
  • 83.93 %
  • assert
  • 94.13 %
  • func
  • 92.83 %
  • line
  • 97.28 %
  • branch
  • 93.85 %
  • cond
  • 79.43 %
  • toggle
  • 85.54 %
  • FSM
  • 63.55 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 1.380s 81.048us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 0.800s 52.613us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 0.950s 27.765us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.710s 214.108us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.050s 17.417us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.020s 33.212us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 0.950s 27.765us 1 1 100.00
lc_ctrl_csr_aliasing 1.050s 17.417us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 3.730s 256.665us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 5.770s 2154.434us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 0.860s 39.734us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 1.190s 22.976us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 6.250s 326.539us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 4.370s 317.060us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 6.250s 326.539us 1 1 100.00
lc_ctrl_prog_failure 1.190s 22.976us 1 1 100.00
lc_ctrl_errors 4.370s 317.060us 1 1 100.00
lc_ctrl_security_escalation 3.620s 630.981us 1 1 100.00
lc_ctrl_jtag_state_failure 27.740s 12414.347us 1 1 100.00
lc_ctrl_jtag_prog_failure 1.830s 296.771us 1 1 100.00
lc_ctrl_jtag_errors 29.560s 41704.100us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 3.970s 867.578us 1 1 100.00
lc_ctrl_jtag_state_post_trans 5.640s 1168.329us 1 1 100.00
lc_ctrl_jtag_prog_failure 1.830s 296.771us 1 1 100.00
lc_ctrl_jtag_errors 29.560s 41704.100us 1 1 100.00
lc_ctrl_jtag_access 4.860s 924.098us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 8.790s 2375.085us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 1.680s 83.194us 1 1 100.00
lc_ctrl_jtag_csr_rw 0.920s 61.106us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 6.550s 4415.366us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 2.660s 1343.722us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 0.950s 93.120us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 1.350s 215.777us 1 1 100.00
lc_ctrl_jtag_alert_test 1.020s 60.179us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 2.710s 2312.968us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 1.020s 19.924us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 22.380s 1700.065us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 0.890s 84.628us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 2.670s 385.087us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 2.670s 385.087us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.800s 52.613us 1 1 100.00
lc_ctrl_csr_rw 0.950s 27.765us 1 1 100.00
lc_ctrl_csr_aliasing 1.050s 17.417us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.150s 94.577us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.800s 52.613us 1 1 100.00
lc_ctrl_csr_rw 0.950s 27.765us 1 1 100.00
lc_ctrl_csr_aliasing 1.050s 17.417us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.150s 94.577us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 5.690s 224.581us 1 1 100.00
lc_ctrl_tl_intg_err 1.700s 501.069us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 1.700s 501.069us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 5.770s 2154.434us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 6.250s 326.539us 1 1 100.00
lc_ctrl_sec_cm 5.690s 224.581us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 6.250s 326.539us 1 1 100.00
lc_ctrl_sec_cm 5.690s 224.581us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 6.250s 326.539us 1 1 100.00
lc_ctrl_sec_cm 5.690s 224.581us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 6.250s 326.539us 1 1 100.00
lc_ctrl_sec_cm 5.690s 224.581us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 6.250s 326.539us 1 1 100.00
lc_ctrl_sec_cm 5.690s 224.581us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 6.250s 326.539us 1 1 100.00
lc_ctrl_sec_cm 5.690s 224.581us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 6.250s 326.539us 1 1 100.00
lc_ctrl_sec_cm 5.690s 224.581us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 6.250s 326.539us 1 1 100.00
lc_ctrl_sec_cm 5.690s 224.581us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 3.620s 630.981us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 3.730s 256.665us 1 1 100.00
lc_ctrl_jtag_state_post_trans 5.640s 1168.329us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 4.630s 1241.221us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 4.630s 1241.221us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 6.080s 1002.628us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 3.430s 270.160us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 3.430s 270.160us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
lc_ctrl_stress_all_with_rand_reset 17.640s 3242.051us 1 1 100.00