Simulation Results: lc_ctrl/volatile_unlock_enabled

 
06/08/2026 15:30:30 DVSim: v1.50.0 sha: 377160a json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 90.26 %
  • code
  • 83.94 %
  • assert
  • 94.55 %
  • func
  • 92.29 %
  • line
  • 97.04 %
  • branch
  • 93.23 %
  • cond
  • 79.20 %
  • toggle
  • 84.82 %
  • FSM
  • 65.42 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 1.570s 413.941us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 0.740s 20.624us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 0.720s 56.134us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 0.920s 89.668us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 0.980s 20.856us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 0.930s 19.274us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 0.720s 56.134us 1 1 100.00
lc_ctrl_csr_aliasing 0.980s 20.856us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 5.650s 80.944us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 12.670s 457.549us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 0.770s 12.281us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 1.350s 47.751us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 8.800s 662.934us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 5.010s 4478.661us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 8.800s 662.934us 1 1 100.00
lc_ctrl_prog_failure 1.350s 47.751us 1 1 100.00
lc_ctrl_errors 5.010s 4478.661us 1 1 100.00
lc_ctrl_security_escalation 5.150s 825.921us 1 1 100.00
lc_ctrl_jtag_state_failure 15.470s 14411.057us 1 1 100.00
lc_ctrl_jtag_prog_failure 3.650s 315.642us 1 1 100.00
lc_ctrl_jtag_errors 22.120s 11359.418us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 3.780s 1629.484us 1 1 100.00
lc_ctrl_jtag_state_post_trans 9.240s 446.997us 1 1 100.00
lc_ctrl_jtag_prog_failure 3.650s 315.642us 1 1 100.00
lc_ctrl_jtag_errors 22.120s 11359.418us 1 1 100.00
lc_ctrl_jtag_access 1.050s 143.249us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 10.570s 14824.472us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 1.510s 298.522us 1 1 100.00
lc_ctrl_jtag_csr_rw 0.970s 307.920us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 4.270s 2207.185us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 7.290s 5670.234us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 0.980s 52.870us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 1.090s 204.978us 1 1 100.00
lc_ctrl_jtag_alert_test 0.950s 188.192us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 8.450s 1284.142us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 0.900s 22.971us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 86.040s 21339.315us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 0.840s 22.010us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 1.810s 146.402us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 1.810s 146.402us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.740s 20.624us 1 1 100.00
lc_ctrl_csr_rw 0.720s 56.134us 1 1 100.00
lc_ctrl_csr_aliasing 0.980s 20.856us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.220s 44.974us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.740s 20.624us 1 1 100.00
lc_ctrl_csr_rw 0.720s 56.134us 1 1 100.00
lc_ctrl_csr_aliasing 0.980s 20.856us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.220s 44.974us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 6.160s 852.724us 1 1 100.00
lc_ctrl_tl_intg_err 1.630s 301.356us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 1.630s 301.356us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 12.670s 457.549us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 8.800s 662.934us 1 1 100.00
lc_ctrl_sec_cm 6.160s 852.724us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 8.800s 662.934us 1 1 100.00
lc_ctrl_sec_cm 6.160s 852.724us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 8.800s 662.934us 1 1 100.00
lc_ctrl_sec_cm 6.160s 852.724us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 8.800s 662.934us 1 1 100.00
lc_ctrl_sec_cm 6.160s 852.724us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 8.800s 662.934us 1 1 100.00
lc_ctrl_sec_cm 6.160s 852.724us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 8.800s 662.934us 1 1 100.00
lc_ctrl_sec_cm 6.160s 852.724us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 8.800s 662.934us 1 1 100.00
lc_ctrl_sec_cm 6.160s 852.724us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 8.800s 662.934us 1 1 100.00
lc_ctrl_sec_cm 6.160s 852.724us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 5.150s 825.921us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 5.650s 80.944us 1 1 100.00
lc_ctrl_jtag_state_post_trans 9.240s 446.997us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 5.370s 1436.513us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 5.370s 1436.513us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 5.160s 383.108us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 4.440s 318.516us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 4.440s 318.516us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 24.920s 1332.786us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1286) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
lc_ctrl_stress_all_with_rand_reset 71199391289794810034214938293275144925820756524864107806498672754042470395905 426
UVM_INFO @ 1332786213 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---