Simulation Results: otp_ctrl

 
06/08/2026 15:30:30 DVSim: v1.50.0 sha: 377160a json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 81.71 %
  • code
  • 77.69 %
  • assert
  • 94.76 %
  • func
  • 72.69 %
  • line
  • 88.47 %
  • branch
  • 83.26 %
  • cond
  • 90.27 %
  • toggle
  • 81.66 %
  • FSM
  • 44.79 %
Validation stages
V1
100.00%
V2
95.00%
V2S
88.89%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
otp_ctrl_wake_up 1.680s 797.100us 1 1 100.00
smoke 1 1 100.00
otp_ctrl_smoke 3.720s 714.501us 1 1 100.00
csr_hw_reset 1 1 100.00
otp_ctrl_csr_hw_reset 2.060s 1061.227us 1 1 100.00
csr_rw 1 1 100.00
otp_ctrl_csr_rw 1.600s 49.602us 1 1 100.00
csr_bit_bash 1 1 100.00
otp_ctrl_csr_bit_bash 5.240s 685.490us 1 1 100.00
csr_aliasing 1 1 100.00
otp_ctrl_csr_aliasing 3.390s 294.902us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otp_ctrl_csr_mem_rw_with_rand_reset 2.170s 115.540us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otp_ctrl_csr_rw 1.600s 49.602us 1 1 100.00
otp_ctrl_csr_aliasing 3.390s 294.902us 1 1 100.00
mem_walk 1 1 100.00
otp_ctrl_mem_walk 1.230s 139.659us 1 1 100.00
mem_partial_access 1 1 100.00
otp_ctrl_mem_partial_access 1.130s 86.503us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dai_access_partition_walk 1 1 100.00
otp_ctrl_partition_walk 13.040s 1447.903us 1 1 100.00
init_fail 1 1 100.00
otp_ctrl_init_fail 3.500s 578.861us 1 1 100.00
partition_check 2 2 100.00
otp_ctrl_background_chks 16.350s 12760.961us 1 1 100.00
otp_ctrl_check_fail 4.240s 2726.075us 1 1 100.00
regwen_during_otp_init 1 1 100.00
otp_ctrl_regwen 2.500s 98.498us 1 1 100.00
partition_lock 1 1 100.00
otp_ctrl_dai_lock 18.320s 1433.418us 1 1 100.00
interface_key_check 1 1 100.00
otp_ctrl_parallel_key_req 4.700s 281.617us 1 1 100.00
lc_interactions 2 2 100.00
otp_ctrl_parallel_lc_req 9.210s 451.603us 1 1 100.00
otp_ctrl_parallel_lc_esc 7.520s 266.509us 1 1 100.00
otp_dai_errors 1 1 100.00
otp_ctrl_dai_errs 14.020s 1572.075us 1 1 100.00
otp_macro_errors 0 1 0.00
otp_ctrl_macro_errs 13.820s 1703.249us 0 1 0.00
test_access 1 1 100.00
otp_ctrl_test_access 28.470s 23408.024us 1 1 100.00
stress_all 1 1 100.00
otp_ctrl_stress_all 81.060s 13009.975us 1 1 100.00
intr_test 1 1 100.00
otp_ctrl_intr_test 1.270s 78.190us 1 1 100.00
alert_test 1 1 100.00
otp_ctrl_alert_test 1.410s 53.222us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otp_ctrl_tl_errors 4.440s 1435.552us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otp_ctrl_tl_errors 4.440s 1435.552us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otp_ctrl_csr_hw_reset 2.060s 1061.227us 1 1 100.00
otp_ctrl_csr_rw 1.600s 49.602us 1 1 100.00
otp_ctrl_csr_aliasing 3.390s 294.902us 1 1 100.00
otp_ctrl_same_csr_outstanding 1.580s 183.631us 1 1 100.00
tl_d_partial_access 4 4 100.00
otp_ctrl_csr_hw_reset 2.060s 1061.227us 1 1 100.00
otp_ctrl_csr_rw 1.600s 49.602us 1 1 100.00
otp_ctrl_csr_aliasing 3.390s 294.902us 1 1 100.00
otp_ctrl_same_csr_outstanding 1.580s 183.631us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 1 1 100.00
otp_ctrl_sec_cm 308.930s 178863.469us 1 1 100.00
tl_intg_err 2 2 100.00
otp_ctrl_sec_cm 308.930s 178863.469us 1 1 100.00
otp_ctrl_tl_intg_err 11.960s 10343.400us 1 1 100.00
prim_count_check 1 1 100.00
otp_ctrl_sec_cm 308.930s 178863.469us 1 1 100.00
prim_fsm_check 1 1 100.00
otp_ctrl_sec_cm 308.930s 178863.469us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otp_ctrl_tl_intg_err 11.960s 10343.400us 1 1 100.00
sec_cm_secret_mem_scramble 1 1 100.00
otp_ctrl_smoke 3.720s 714.501us 1 1 100.00
sec_cm_part_mem_digest 1 1 100.00
otp_ctrl_smoke 3.720s 714.501us 1 1 100.00
sec_cm_dai_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 308.930s 178863.469us 1 1 100.00
sec_cm_kdi_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 308.930s 178863.469us 1 1 100.00
sec_cm_lci_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 308.930s 178863.469us 1 1 100.00
sec_cm_part_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 308.930s 178863.469us 1 1 100.00
sec_cm_scrmbl_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 308.930s 178863.469us 1 1 100.00
sec_cm_timer_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 308.930s 178863.469us 1 1 100.00
sec_cm_dai_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 308.930s 178863.469us 1 1 100.00
sec_cm_kdi_seed_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 308.930s 178863.469us 1 1 100.00
sec_cm_kdi_entropy_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 308.930s 178863.469us 1 1 100.00
sec_cm_lci_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 308.930s 178863.469us 1 1 100.00
sec_cm_part_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 308.930s 178863.469us 1 1 100.00
sec_cm_scrmbl_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 308.930s 178863.469us 1 1 100.00
sec_cm_timer_integ_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 308.930s 178863.469us 1 1 100.00
sec_cm_timer_cnsty_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 308.930s 178863.469us 1 1 100.00
sec_cm_timer_lfsr_redun 1 1 100.00
otp_ctrl_sec_cm 308.930s 178863.469us 1 1 100.00
sec_cm_dai_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 7.520s 266.509us 1 1 100.00
otp_ctrl_sec_cm 308.930s 178863.469us 1 1 100.00
sec_cm_lci_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 7.520s 266.509us 1 1 100.00
sec_cm_kdi_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 7.520s 266.509us 1 1 100.00
sec_cm_part_fsm_local_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 7.520s 266.509us 1 1 100.00
otp_ctrl_macro_errs 13.820s 1703.249us 0 1 0.00
sec_cm_scrmbl_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 7.520s 266.509us 1 1 100.00
sec_cm_timer_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 7.520s 266.509us 1 1 100.00
otp_ctrl_sec_cm 308.930s 178863.469us 1 1 100.00
sec_cm_dai_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 7.520s 266.509us 1 1 100.00
otp_ctrl_sec_cm 308.930s 178863.469us 1 1 100.00
sec_cm_lci_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 7.520s 266.509us 1 1 100.00
sec_cm_kdi_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 7.520s 266.509us 1 1 100.00
sec_cm_part_fsm_global_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 7.520s 266.509us 1 1 100.00
otp_ctrl_macro_errs 13.820s 1703.249us 0 1 0.00
sec_cm_scrmbl_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 7.520s 266.509us 1 1 100.00
sec_cm_timer_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 7.520s 266.509us 1 1 100.00
otp_ctrl_sec_cm 308.930s 178863.469us 1 1 100.00
sec_cm_part_data_reg_integrity 1 1 100.00
otp_ctrl_init_fail 3.500s 578.861us 1 1 100.00
sec_cm_part_data_reg_bkgn_chk 1 1 100.00
otp_ctrl_check_fail 4.240s 2726.075us 1 1 100.00
sec_cm_part_mem_regren 1 1 100.00
otp_ctrl_dai_lock 18.320s 1433.418us 1 1 100.00
sec_cm_part_mem_sw_unreadable 1 1 100.00
otp_ctrl_dai_lock 18.320s 1433.418us 1 1 100.00
sec_cm_part_mem_sw_unwritable 1 1 100.00
otp_ctrl_dai_lock 18.320s 1433.418us 1 1 100.00
sec_cm_lc_part_mem_sw_noaccess 1 1 100.00
otp_ctrl_dai_lock 18.320s 1433.418us 1 1 100.00
sec_cm_access_ctrl_mubi 1 1 100.00
otp_ctrl_dai_lock 18.320s 1433.418us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
otp_ctrl_smoke 3.720s 714.501us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
otp_ctrl_dai_lock 18.320s 1433.418us 1 1 100.00
sec_cm_test_bus_lc_gated 1 1 100.00
otp_ctrl_smoke 3.720s 714.501us 1 1 100.00
sec_cm_test_tl_lc_gate_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 308.930s 178863.469us 1 1 100.00
sec_cm_direct_access_config_regwen 1 1 100.00
otp_ctrl_regwen 2.500s 98.498us 1 1 100.00
sec_cm_check_trigger_config_regwen 1 1 100.00
otp_ctrl_smoke 3.720s 714.501us 1 1 100.00
sec_cm_check_config_regwen 1 1 100.00
otp_ctrl_smoke 3.720s 714.501us 1 1 100.00
sec_cm_macro_mem_integrity 0 1 0.00
otp_ctrl_macro_errs 13.820s 1703.249us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
otp_ctrl_low_freq_read 1 1 100.00
otp_ctrl_low_freq_read 15.260s 8765.332us 1 1 100.00
stress_all_with_rand_reset 0 1 0.00
otp_ctrl_stress_all_with_rand_reset 49.900s 9618.521us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (otp_ctrl_scoreboard.sv:1208) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* 1 test run
otp_ctrl_macro_errs 104093285819693784479064889143514180981632280147455002286555298368919281126109 3870
UVM_INFO @ 1703249342 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1831) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) d_data mismatch when d_error = * 1 test run
otp_ctrl_stress_all_with_rand_reset 28180061280090694750410594624779488254006406650341388132157791825347747996540 7807
UVM_INFO @ 9618520538 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---