Simulation Results: pwrmgr

 
06/08/2026 15:30:30 DVSim: v1.50.0 sha: 377160a json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.37 %
  • code
  • 95.79 %
  • assert
  • 98.96 %
  • func
  • 97.36 %
  • line
  • 99.09 %
  • branch
  • 96.37 %
  • cond
  • 96.32 %
  • toggle
  • 91.15 %
  • FSM
  • 96.00 %
Validation stages
V1
100.00%
V2
93.33%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
pwrmgr_smoke 0.610s 46.016us 1 1 100.00
csr_hw_reset 1 1 100.00
pwrmgr_csr_hw_reset 0.660s 31.032us 1 1 100.00
csr_rw 1 1 100.00
pwrmgr_csr_rw 0.750s 170.159us 1 1 100.00
csr_bit_bash 1 1 100.00
pwrmgr_csr_bit_bash 2.180s 107.220us 1 1 100.00
csr_aliasing 1 1 100.00
pwrmgr_csr_aliasing 0.910s 315.422us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
pwrmgr_csr_mem_rw_with_rand_reset 0.980s 123.874us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
pwrmgr_csr_rw 0.750s 170.159us 1 1 100.00
pwrmgr_csr_aliasing 0.910s 315.422us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
wakeup 1 1 100.00
pwrmgr_wakeup 0.660s 109.836us 1 1 100.00
control_clks 1 1 100.00
pwrmgr_wakeup 0.660s 109.836us 1 1 100.00
aborted_low_power 2 2 100.00
pwrmgr_aborted_low_power 0.860s 64.198us 1 1 100.00
pwrmgr_lowpower_invalid 0.660s 42.746us 1 1 100.00
reset 2 2 100.00
pwrmgr_reset 0.650s 56.164us 1 1 100.00
pwrmgr_reset_invalid 0.700s 205.165us 1 1 100.00
main_power_glitch_reset 1 1 100.00
pwrmgr_reset 0.650s 56.164us 1 1 100.00
reset_wakeup_race 1 1 100.00
pwrmgr_wakeup_reset 0.710s 90.204us 1 1 100.00
lowpower_wakeup_race 1 1 100.00
pwrmgr_lowpower_wakeup_race 0.750s 121.519us 1 1 100.00
disable_rom_integrity_check 1 1 100.00
pwrmgr_disable_rom_integrity_check 0.790s 39.424us 1 1 100.00
stress_all 0 1 0.00
pwrmgr_stress_all 14.350s 10993.298us 0 1 0.00
intr_test 1 1 100.00
pwrmgr_intr_test 0.550s 34.797us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
pwrmgr_tl_errors 1.350s 73.792us 1 1 100.00
tl_d_illegal_access 1 1 100.00
pwrmgr_tl_errors 1.350s 73.792us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
pwrmgr_csr_hw_reset 0.660s 31.032us 1 1 100.00
pwrmgr_csr_rw 0.750s 170.159us 1 1 100.00
pwrmgr_csr_aliasing 0.910s 315.422us 1 1 100.00
pwrmgr_same_csr_outstanding 0.790s 21.063us 1 1 100.00
tl_d_partial_access 4 4 100.00
pwrmgr_csr_hw_reset 0.660s 31.032us 1 1 100.00
pwrmgr_csr_rw 0.750s 170.159us 1 1 100.00
pwrmgr_csr_aliasing 0.910s 315.422us 1 1 100.00
pwrmgr_same_csr_outstanding 0.790s 21.063us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
pwrmgr_tl_intg_err 1.270s 284.009us 1 1 100.00
pwrmgr_sec_cm 1.090s 2060.574us 1 1 100.00
prim_count_check 1 1 100.00
pwrmgr_sec_cm 1.090s 2060.574us 1 1 100.00
prim_fsm_check 1 1 100.00
pwrmgr_sec_cm 1.090s 2060.574us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
pwrmgr_tl_intg_err 1.270s 284.009us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
pwrmgr_sec_cm_lc_ctrl_intersig_mubi 1.470s 991.143us 1 1 100.00
sec_cm_rom_ctrl_intersig_mubi 2 2 100.00
pwrmgr_wakeup_reset 0.710s 90.204us 1 1 100.00
pwrmgr_repeat_wakeup_reset 1.950s 828.773us 1 1 100.00
sec_cm_rstmgr_intersig_mubi 1 1 100.00
pwrmgr_sec_cm_rstmgr_intersig_mubi 0.820s 188.860us 1 1 100.00
sec_cm_esc_rx_clk_bkgn_chk 1 1 100.00
pwrmgr_esc_clk_rst_malfunc 0.640s 32.933us 1 1 100.00
sec_cm_esc_rx_clk_local_esc 1 1 100.00
pwrmgr_sec_cm 1.090s 2060.574us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
pwrmgr_sec_cm 1.090s 2060.574us 1 1 100.00
sec_cm_fsm_terminal 1 1 100.00
pwrmgr_sec_cm 1.090s 2060.574us 1 1 100.00
sec_cm_ctrl_flow_global_esc 1 1 100.00
pwrmgr_global_esc 0.670s 94.867us 1 1 100.00
sec_cm_main_pd_rst_local_esc 1 1 100.00
pwrmgr_glitch 0.670s 40.262us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
pwrmgr_sec_cm_ctrl_config_regwen 0.750s 145.048us 1 1 100.00
sec_cm_wakeup_config_regwen 1 1 100.00
pwrmgr_csr_rw 0.750s 170.159us 1 1 100.00
sec_cm_reset_config_regwen 1 1 100.00
pwrmgr_csr_rw 0.750s 170.159us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
escalation_timeout 1 1 100.00
pwrmgr_escalation_timeout 0.710s 470.547us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
pwrmgr_stress_all_with_rand_reset 14.880s 7864.727us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (pwrmgr_reset_vseq.sv:62) [pwrmgr_reset_vseq] wait timeout occurred! 1 test run
pwrmgr_stress_all 63889626304793062336618789159067982291105534642471040521824099933790050887128 687
UVM_INFO @ 10993298354 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---