Simulation Results: rstmgr

 
06/08/2026 15:30:30 DVSim: v1.50.0 sha: 377160a json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.15 %
  • code
  • 99.15 %
  • assert
  • 98.53 %
  • func
  • 96.77 %
  • line
  • 99.51 %
  • branch
  • 99.83 %
  • cond
  • 98.26 %
  • toggle
  • 99.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rstmgr_smoke 1.250s 272.331us 1 1 100.00
csr_hw_reset 1 1 100.00
rstmgr_csr_hw_reset 0.800s 100.822us 1 1 100.00
csr_rw 1 1 100.00
rstmgr_csr_rw 0.790s 77.576us 1 1 100.00
csr_bit_bash 1 1 100.00
rstmgr_csr_bit_bash 2.740s 382.500us 1 1 100.00
csr_aliasing 1 1 100.00
rstmgr_csr_aliasing 1.520s 240.992us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rstmgr_csr_mem_rw_with_rand_reset 0.930s 142.861us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rstmgr_csr_rw 0.790s 77.576us 1 1 100.00
rstmgr_csr_aliasing 1.520s 240.992us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_stretcher 1 1 100.00
rstmgr_por_stretcher 0.850s 177.915us 1 1 100.00
sw_rst 1 1 100.00
rstmgr_sw_rst 1.750s 432.368us 1 1 100.00
sw_rst_reset_race 1 1 100.00
rstmgr_sw_rst_reset_race 1.080s 196.874us 1 1 100.00
reset_info 1 1 100.00
rstmgr_reset 6.150s 2299.289us 1 1 100.00
cpu_info 1 1 100.00
rstmgr_reset 6.150s 2299.289us 1 1 100.00
alert_info 1 1 100.00
rstmgr_reset 6.150s 2299.289us 1 1 100.00
reset_info_capture 1 1 100.00
rstmgr_reset 6.150s 2299.289us 1 1 100.00
stress_all 1 1 100.00
rstmgr_stress_all 16.980s 5994.457us 1 1 100.00
alert_test 1 1 100.00
rstmgr_alert_test 0.720s 67.945us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rstmgr_tl_errors 1.670s 302.248us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rstmgr_tl_errors 1.670s 302.248us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rstmgr_csr_hw_reset 0.800s 100.822us 1 1 100.00
rstmgr_csr_rw 0.790s 77.576us 1 1 100.00
rstmgr_csr_aliasing 1.520s 240.992us 1 1 100.00
rstmgr_same_csr_outstanding 0.940s 128.815us 1 1 100.00
tl_d_partial_access 4 4 100.00
rstmgr_csr_hw_reset 0.800s 100.822us 1 1 100.00
rstmgr_csr_rw 0.790s 77.576us 1 1 100.00
rstmgr_csr_aliasing 1.520s 240.992us 1 1 100.00
rstmgr_same_csr_outstanding 0.940s 128.815us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rstmgr_sec_cm 18.990s 16919.369us 1 1 100.00
rstmgr_tl_intg_err 2.400s 990.374us 1 1 100.00
prim_count_check 1 1 100.00
rstmgr_sec_cm 18.990s 16919.369us 1 1 100.00
prim_fsm_check 1 1 100.00
rstmgr_sec_cm 18.990s 16919.369us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rstmgr_tl_intg_err 2.400s 990.374us 1 1 100.00
sec_cm_scan_intersig_mubi 1 1 100.00
rstmgr_sec_cm_scan_intersig_mubi 1.070s 208.990us 1 1 100.00
sec_cm_leaf_rst_bkgn_chk 1 1 100.00
rstmgr_leaf_rst_cnsty 4.450s 1411.873us 1 1 100.00
sec_cm_leaf_rst_shadow 1 1 100.00
rstmgr_leaf_rst_shadow_attack 0.990s 302.150us 1 1 100.00
sec_cm_leaf_fsm_sparse 1 1 100.00
rstmgr_sec_cm 18.990s 16919.369us 1 1 100.00
sec_cm_sw_rst_config_regwen 1 1 100.00
rstmgr_csr_rw 0.790s 77.576us 1 1 100.00
sec_cm_dump_ctrl_config_regwen 1 1 100.00
rstmgr_csr_rw 0.790s 77.576us 1 1 100.00