Simulation Results: rv_timer

 
06/08/2026 15:30:30 DVSim: v1.50.0 sha: 377160a json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.39 %
  • code
  • 100.00 %
  • assert
  • 96.82 %
  • func
  • 92.35 %
  • line
  • 100.00 %
  • branch
  • 100.00 %
  • cond
  • 100.00 %
  • toggle
  • 100.00 %
Validation stages
V1
100.00%
V2
90.91%
V2S
100.00%
V3
33.33%
Testpoint Test Max Runtime Sim Time Pass Total %
random 1 1 100.00
rv_timer_random 0.630s 37.122us 1 1 100.00
csr_hw_reset 1 1 100.00
rv_timer_csr_hw_reset 0.710s 16.108us 1 1 100.00
csr_rw 1 1 100.00
rv_timer_csr_rw 0.610s 24.670us 1 1 100.00
csr_bit_bash 1 1 100.00
rv_timer_csr_bit_bash 2.130s 346.466us 1 1 100.00
csr_aliasing 1 1 100.00
rv_timer_csr_aliasing 0.750s 26.377us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rv_timer_csr_mem_rw_with_rand_reset 0.860s 36.465us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rv_timer_csr_rw 0.610s 24.670us 1 1 100.00
rv_timer_csr_aliasing 0.750s 26.377us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
random_reset 0 1 0.00
rv_timer_random_reset 0.700s 104.881us 0 1 0.00
disabled 1 1 100.00
rv_timer_disabled 1.230s 3289.890us 1 1 100.00
cfg_update_on_fly 1 1 100.00
rv_timer_cfg_update_on_fly 15.040s 57103.721us 1 1 100.00
no_interrupt_test 1 1 100.00
rv_timer_cfg_update_on_fly 15.040s 57103.721us 1 1 100.00
stress 1 1 100.00
rv_timer_stress_all 1.750s 4405.900us 1 1 100.00
alert_test 1 1 100.00
rv_timer_alert_test 0.660s 17.088us 1 1 100.00
intr_test 1 1 100.00
rv_timer_intr_test 0.680s 29.112us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rv_timer_tl_errors 0.880s 53.529us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rv_timer_tl_errors 0.880s 53.529us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rv_timer_csr_hw_reset 0.710s 16.108us 1 1 100.00
rv_timer_csr_rw 0.610s 24.670us 1 1 100.00
rv_timer_csr_aliasing 0.750s 26.377us 1 1 100.00
rv_timer_same_csr_outstanding 0.590s 91.399us 1 1 100.00
tl_d_partial_access 4 4 100.00
rv_timer_csr_hw_reset 0.710s 16.108us 1 1 100.00
rv_timer_csr_rw 0.610s 24.670us 1 1 100.00
rv_timer_csr_aliasing 0.750s 26.377us 1 1 100.00
rv_timer_same_csr_outstanding 0.590s 91.399us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rv_timer_sec_cm 0.680s 37.806us 1 1 100.00
rv_timer_tl_intg_err 1.060s 100.944us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rv_timer_tl_intg_err 1.060s 100.944us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
min_value 0 1 0.00
rv_timer_min 0.720s 416.638us 0 1 0.00
max_value 0 1 0.00
rv_timer_max 0.670s 435.825us 0 1 0.00
stress_all_with_rand_reset 1 1 100.00
rv_timer_stress_all_with_rand_reset 13.100s 1723.833us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * 2 test runs
rv_timer_min 46992708594700867089192210428097322991908110742428267246324776083957694217158 77
UVM_INFO @ 416637720 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 103854885661011163135023629834004426473786952263154306567071764259354440871199 75
UVM_INFO @ 104881268 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_timer_scoreboard.sv:231) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) 1 test run
rv_timer_max 98572136710498175226993126086736681012206159174957524615857071117008832198192 76
UVM_INFO @ 435824655 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---