Simulation Results: spi_device/1r1w

 
06/08/2026 15:30:30 DVSim: v1.50.0 sha: 377160a json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 86.17 %
  • code
  • 93.90 %
  • assert
  • 94.78 %
  • func
  • 69.84 %
  • line
  • 98.88 %
  • branch
  • 98.23 %
  • cond
  • 96.10 %
  • toggle
  • 86.92 %
  • FSM
  • 89.36 %
Validation stages
V1
100.00%
V2
92.59%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_device_flash_and_tpm 83.590s 27451.352us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_device_csr_hw_reset 1.180s 44.003us 1 1 100.00
csr_rw 1 1 100.00
spi_device_csr_rw 1.390s 495.708us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_device_csr_bit_bash 18.100s 1995.048us 1 1 100.00
csr_aliasing 1 1 100.00
spi_device_csr_aliasing 5.900s 381.621us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_device_csr_mem_rw_with_rand_reset 2.250s 171.008us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_device_csr_rw 1.390s 495.708us 1 1 100.00
spi_device_csr_aliasing 5.900s 381.621us 1 1 100.00
mem_walk 1 1 100.00
spi_device_mem_walk 0.700s 17.199us 1 1 100.00
mem_partial_access 1 1 100.00
spi_device_mem_partial_access 1.380s 179.716us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
csb_read 1 1 100.00
spi_device_csb_read 0.730s 17.479us 1 1 100.00
mem_parity 0 1 0.00
spi_device_mem_parity 0.700s 7.057us 0 1 0.00
mem_cfg 0 1 0.00
spi_device_ram_cfg 0.930s 2.878us 0 1 0.00
tpm_read 1 1 100.00
spi_device_tpm_rw 0.840s 34.333us 1 1 100.00
tpm_write 1 1 100.00
spi_device_tpm_rw 0.840s 34.333us 1 1 100.00
tpm_hw_reg 2 2 100.00
spi_device_tpm_read_hw_reg 10.440s 6742.396us 1 1 100.00
spi_device_tpm_sts_read 0.770s 57.626us 1 1 100.00
tpm_fully_random_case 1 1 100.00
spi_device_tpm_all 16.430s 1518.016us 1 1 100.00
pass_cmd_filtering 2 2 100.00
spi_device_pass_cmd_filtering 9.490s 15377.128us 1 1 100.00
spi_device_flash_all 47.430s 17723.024us 1 1 100.00
pass_addr_translation 2 2 100.00
spi_device_pass_addr_payload_swap 5.940s 8733.853us 1 1 100.00
spi_device_flash_all 47.430s 17723.024us 1 1 100.00
pass_payload_translation 2 2 100.00
spi_device_pass_addr_payload_swap 5.940s 8733.853us 1 1 100.00
spi_device_flash_all 47.430s 17723.024us 1 1 100.00
cmd_info_slots 1 1 100.00
spi_device_flash_all 47.430s 17723.024us 1 1 100.00
cmd_read_status 2 2 100.00
spi_device_intercept 2.250s 82.045us 1 1 100.00
spi_device_flash_all 47.430s 17723.024us 1 1 100.00
cmd_read_jedec 2 2 100.00
spi_device_intercept 2.250s 82.045us 1 1 100.00
spi_device_flash_all 47.430s 17723.024us 1 1 100.00
cmd_read_sfdp 2 2 100.00
spi_device_intercept 2.250s 82.045us 1 1 100.00
spi_device_flash_all 47.430s 17723.024us 1 1 100.00
cmd_fast_read 2 2 100.00
spi_device_intercept 2.250s 82.045us 1 1 100.00
spi_device_flash_all 47.430s 17723.024us 1 1 100.00
cmd_read_pipeline 2 2 100.00
spi_device_intercept 2.250s 82.045us 1 1 100.00
spi_device_flash_all 47.430s 17723.024us 1 1 100.00
flash_cmd_upload 1 1 100.00
spi_device_upload 2.900s 3611.660us 1 1 100.00
mailbox_command 1 1 100.00
spi_device_mailbox 5.780s 2281.051us 1 1 100.00
mailbox_cross_outside_command 1 1 100.00
spi_device_mailbox 5.780s 2281.051us 1 1 100.00
mailbox_cross_inside_command 1 1 100.00
spi_device_mailbox 5.780s 2281.051us 1 1 100.00
cmd_read_buffer 2 2 100.00
spi_device_flash_mode 25.290s 5386.326us 1 1 100.00
spi_device_read_buffer_direct 6.280s 1019.054us 1 1 100.00
cmd_dummy_cycle 2 2 100.00
spi_device_mailbox 5.780s 2281.051us 1 1 100.00
spi_device_flash_all 47.430s 17723.024us 1 1 100.00
quad_spi 1 1 100.00
spi_device_flash_all 47.430s 17723.024us 1 1 100.00
dual_spi 1 1 100.00
spi_device_flash_all 47.430s 17723.024us 1 1 100.00
4b_3b_feature 1 1 100.00
spi_device_cfg_cmd 1.980s 561.542us 1 1 100.00
write_enable_disable 1 1 100.00
spi_device_cfg_cmd 1.980s 561.542us 1 1 100.00
flash_mode_ignore_cmds 1 1 100.00
spi_device_flash_mode_ignore_cmds 5.770s 7992.461us 1 1 100.00
TPM_with_flash_or_passthrough_mode 1 1 100.00
spi_device_flash_and_tpm 83.590s 27451.352us 1 1 100.00
tpm_and_flash_trans_with_min_inactive_time 1 1 100.00
spi_device_flash_and_tpm_min_idle 45.970s 6923.513us 1 1 100.00
stress_all 1 1 100.00
spi_device_stress_all 387.380s 140766.729us 1 1 100.00
alert_test 1 1 100.00
spi_device_alert_test 0.740s 41.586us 1 1 100.00
intr_test 1 1 100.00
spi_device_intr_test 0.660s 33.572us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_device_tl_errors 3.010s 66.587us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_device_tl_errors 3.010s 66.587us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_device_csr_hw_reset 1.180s 44.003us 1 1 100.00
spi_device_csr_rw 1.390s 495.708us 1 1 100.00
spi_device_csr_aliasing 5.900s 381.621us 1 1 100.00
spi_device_same_csr_outstanding 3.470s 2224.714us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_device_csr_hw_reset 1.180s 44.003us 1 1 100.00
spi_device_csr_rw 1.390s 495.708us 1 1 100.00
spi_device_csr_aliasing 5.900s 381.621us 1 1 100.00
spi_device_same_csr_outstanding 3.470s 2224.714us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_device_sec_cm 1.140s 748.717us 1 1 100.00
spi_device_tl_intg_err 5.960s 349.362us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_device_tl_intg_err 5.960s 349.362us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*]) 1 test run
spi_device_mem_parity 435367398121998181077833188881957607700996018164486178705842740132109049054 76
Either the name is incorrect, or you may not have PLI/ACC visibility to that name
UVM_ERROR @ 4640331 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
UVM_ERROR @ 4640331 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[974])
Either the name is incorrect, or you may not have PLI/ACC visibility to that name
UVM_ERROR (spi_device_ram_cfg_vseq.sv:28) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) 1 test run
spi_device_ram_cfg 71265848205809483670388640296995618913882329325713924657056612305618771816363 76
UVM_ERROR @ 809920 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xce [11001110] vs 0x0 [0])
UVM_ERROR @ 838920 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x143 [101000011] vs 0x0 [0])
UVM_ERROR @ 910920 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x6 [110] vs 0x0 [0])
UVM_ERROR @ 996920 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x1aa [110101010] vs 0x0 [0])