Simulation Results: sram_ctrl/main

 
06/08/2026 15:30:30 DVSim: v1.50.0 sha: 377160a json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 96.09 %
  • code
  • 94.98 %
  • assert
  • 97.69 %
  • func
  • 95.60 %
  • block
  • 95.15 %
  • line
  • 95.71 %
  • branch
  • 92.37 %
  • toggle
  • 91.84 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 4.000s 382.389us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 1.000s 240.338us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 2.000s 17.134us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 3.000s 102.779us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 13.984us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 3.000s 383.472us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 2.000s 17.134us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 13.984us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 233.000s 143103.053us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 40.000s 3485.098us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 25.000s 7846.899us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 98.000s 23138.760us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 143.000s 15614.556us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 35.000s 49046.718us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 28.000s 45644.714us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 10.000s 8382.058us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 5.000s 2658.583us 1 1 100.00
sram_ctrl_partial_access_b2b 280.000s 24374.839us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 4.000s 3925.069us 1 1 100.00
sram_ctrl_throughput_w_partial_write 5.000s 4171.029us 1 1 100.00
sram_ctrl_throughput_w_readback 5.000s 725.523us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 12.000s 5689.221us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 3.000s 687.316us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 78.000s 25189.343us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 1.000s 28.939us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 3.000s 73.922us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 3.000s 73.922us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 240.338us 1 1 100.00
sram_ctrl_csr_rw 2.000s 17.134us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 13.984us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 32.425us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 240.338us 1 1 100.00
sram_ctrl_csr_rw 2.000s 17.134us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 13.984us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 32.425us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 23.000s 25233.584us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 3.000s 368.705us 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 159.443us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 3.000s 368.705us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 159.443us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 12.000s 5689.221us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 12.000s 5689.221us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 2.000s 17.134us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 10.000s 8382.058us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 10.000s 8382.058us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 10.000s 8382.058us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 28.000s 45644.714us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 4.000s 2851.772us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 23.000s 25233.584us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 4.000s 2784.942us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 4.000s 382.389us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 4.000s 382.389us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 10.000s 8382.058us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 3.000s 368.705us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 28.000s 45644.714us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 3.000s 368.705us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 368.705us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 4.000s 382.389us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 368.705us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 42.000s 16991.015us 1 1 100.00