Simulation Results: sram_ctrl/ret

 
06/08/2026 15:30:30 DVSim: v1.50.0 sha: 377160a json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 90.70 %
  • code
  • 81.31 %
  • assert
  • 97.81 %
  • func
  • 93.00 %
  • block
  • 92.39 %
  • line
  • 93.26 %
  • branch
  • 86.97 %
  • toggle
  • 78.32 %
  • FSM
  • 66.67 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 1.000s 85.377us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 1.000s 18.516us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 1.000s 10.588us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 2.000s 288.175us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 47.686us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 2.000s 105.152us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 1.000s 10.588us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 47.686us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 5.000s 103.600us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 4.000s 99.076us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 10.000s 1762.089us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 82.000s 1821.417us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 5.000s 145.574us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 19.000s 1239.387us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 5.000s 513.336us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 11.000s 3450.716us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 1.000s 97.016us 1 1 100.00
sram_ctrl_partial_access_b2b 58.000s 1597.196us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 2.000s 73.343us 1 1 100.00
sram_ctrl_throughput_w_partial_write 2.000s 148.251us 1 1 100.00
sram_ctrl_throughput_w_readback 2.000s 69.484us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 6.000s 308.349us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 2.000s 189.342us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 23.000s 4561.908us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 1.000s 27.527us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 3.000s 33.172us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 3.000s 33.172us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 18.516us 1 1 100.00
sram_ctrl_csr_rw 1.000s 10.588us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 47.686us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 24.674us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 18.516us 1 1 100.00
sram_ctrl_csr_rw 1.000s 10.588us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 47.686us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 24.674us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 4.000s 2042.382us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 4.000s 2607.931us 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 1046.543us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 4.000s 2607.931us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 1046.543us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 6.000s 308.349us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 6.000s 308.349us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 1.000s 10.588us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 11.000s 3450.716us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 11.000s 3450.716us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 11.000s 3450.716us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 5.000s 513.336us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 1.000s 34.181us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 4.000s 2042.382us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 2.000s 36.386us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 1.000s 85.377us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 1.000s 85.377us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 11.000s 3450.716us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 4.000s 2607.931us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 5.000s 513.336us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 4.000s 2607.931us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 4.000s 2607.931us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 1.000s 85.377us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 4.000s 2607.931us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 6.000s 411.318us 1 1 100.00