Simulation Results: sysrst_ctrl

 
06/08/2026 15:30:30 DVSim: v1.50.0 sha: 377160a json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 83.55 %
  • code
  • 92.72 %
  • assert
  • 94.44 %
  • func
  • 63.50 %
  • line
  • 97.26 %
  • branch
  • 97.48 %
  • cond
  • 95.13 %
  • toggle
  • 100.00 %
  • FSM
  • 73.72 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sysrst_ctrl_smoke 4.100s 2113.271us 1 1 100.00
input_output_inverted 1 1 100.00
sysrst_ctrl_in_out_inverted 1.180s 2580.316us 1 1 100.00
combo_detect_ec_rst 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst 1.460s 2186.423us 1 1 100.00
combo_detect_ec_rst_with_pre_cond 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst_with_pre_cond 2.530s 2360.347us 1 1 100.00
csr_hw_reset 1 1 100.00
sysrst_ctrl_csr_hw_reset 2.170s 4049.811us 1 1 100.00
csr_rw 1 1 100.00
sysrst_ctrl_csr_rw 3.000s 2079.255us 1 1 100.00
csr_bit_bash 1 1 100.00
sysrst_ctrl_csr_bit_bash 20.350s 39165.099us 1 1 100.00
csr_aliasing 1 1 100.00
sysrst_ctrl_csr_aliasing 4.920s 2257.585us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sysrst_ctrl_csr_mem_rw_with_rand_reset 1.540s 2506.191us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sysrst_ctrl_csr_rw 3.000s 2079.255us 1 1 100.00
sysrst_ctrl_csr_aliasing 4.920s 2257.585us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
combo_detect 1 1 100.00
sysrst_ctrl_combo_detect 36.000s 83794.514us 1 1 100.00
combo_detect_with_pre_cond 1 1 100.00
sysrst_ctrl_combo_detect_with_pre_cond 21.610s 59187.277us 1 1 100.00
auto_block_key_outputs 1 1 100.00
sysrst_ctrl_auto_blk_key_output 1.730s 3313.074us 1 1 100.00
keyboard_input_triggered_interrupt 1 1 100.00
sysrst_ctrl_edge_detect 1.770s 3465.657us 1 1 100.00
pin_output_keyboard_inversion_control 1 1 100.00
sysrst_ctrl_pin_override_test 2.860s 2514.091us 1 1 100.00
pin_input_value_accessibility 1 1 100.00
sysrst_ctrl_pin_access_test 1.790s 2239.315us 1 1 100.00
ec_power_on_reset 1 1 100.00
sysrst_ctrl_ec_pwr_on_rst 2.070s 3767.424us 1 1 100.00
flash_write_protect_output 1 1 100.00
sysrst_ctrl_flash_wr_prot_out 2.150s 2625.330us 1 1 100.00
ultra_low_power_test 1 1 100.00
sysrst_ctrl_ultra_low_pwr 2.980s 2633.956us 1 1 100.00
sysrst_ctrl_feature_disable 1 1 100.00
sysrst_ctrl_feature_disable 16.690s 38427.884us 1 1 100.00
stress_all 1 1 100.00
sysrst_ctrl_stress_all 62.100s 491064.988us 1 1 100.00
alert_test 1 1 100.00
sysrst_ctrl_alert_test 1.340s 2027.923us 1 1 100.00
intr_test 1 1 100.00
sysrst_ctrl_intr_test 1.600s 2021.551us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sysrst_ctrl_tl_errors 5.120s 2116.168us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sysrst_ctrl_tl_errors 5.120s 2116.168us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sysrst_ctrl_csr_hw_reset 2.170s 4049.811us 1 1 100.00
sysrst_ctrl_csr_rw 3.000s 2079.255us 1 1 100.00
sysrst_ctrl_csr_aliasing 4.920s 2257.585us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 13.890s 7401.337us 1 1 100.00
tl_d_partial_access 4 4 100.00
sysrst_ctrl_csr_hw_reset 2.170s 4049.811us 1 1 100.00
sysrst_ctrl_csr_rw 3.000s 2079.255us 1 1 100.00
sysrst_ctrl_csr_aliasing 4.920s 2257.585us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 13.890s 7401.337us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
sysrst_ctrl_sec_cm 9.270s 22109.658us 1 1 100.00
sysrst_ctrl_tl_intg_err 39.500s 22187.690us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sysrst_ctrl_tl_intg_err 39.500s 22187.690us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sysrst_ctrl_stress_all_with_rand_reset 8.170s 4041.071us 1 1 100.00