Simulation Results: uart

 
06/08/2026 15:30:30 DVSim: v1.50.0 sha: 377160a json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 79.02 %
  • code
  • 94.87 %
  • assert
  • 97.12 %
  • func
  • 45.06 %
  • line
  • 98.86 %
  • branch
  • 96.50 %
  • cond
  • 93.47 %
  • toggle
  • 90.64 %
Validation stages
V1
100.00%
V2
90.91%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
uart_smoke 15.120s 6010.811us 1 1 100.00
csr_hw_reset 1 1 100.00
uart_csr_hw_reset 0.610s 16.554us 1 1 100.00
csr_rw 1 1 100.00
uart_csr_rw 0.760s 18.729us 1 1 100.00
csr_bit_bash 1 1 100.00
uart_csr_bit_bash 1.440s 334.081us 1 1 100.00
csr_aliasing 1 1 100.00
uart_csr_aliasing 1.070s 31.095us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
uart_csr_mem_rw_with_rand_reset 0.660s 75.299us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
uart_csr_rw 0.760s 18.729us 1 1 100.00
uart_csr_aliasing 1.070s 31.095us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
base_random_seq 1 1 100.00
uart_tx_rx 20.210s 68009.266us 1 1 100.00
parity 2 2 100.00
uart_smoke 15.120s 6010.811us 1 1 100.00
uart_tx_rx 20.210s 68009.266us 1 1 100.00
parity_error 2 2 100.00
uart_intr 21.300s 100007.183us 1 1 100.00
uart_rx_parity_err 25.920s 31886.605us 1 1 100.00
watermark 2 2 100.00
uart_tx_rx 20.210s 68009.266us 1 1 100.00
uart_intr 21.300s 100007.183us 1 1 100.00
fifo_full 1 1 100.00
uart_fifo_full 271.750s 266010.923us 1 1 100.00
fifo_overflow 1 1 100.00
uart_fifo_overflow 114.640s 106890.921us 1 1 100.00
fifo_reset 1 1 100.00
uart_fifo_reset 62.700s 174589.477us 1 1 100.00
rx_frame_err 1 1 100.00
uart_intr 21.300s 100007.183us 1 1 100.00
rx_break_err 1 1 100.00
uart_intr 21.300s 100007.183us 1 1 100.00
rx_timeout 1 1 100.00
uart_intr 21.300s 100007.183us 1 1 100.00
perf 1 1 100.00
uart_perf 35.140s 5187.397us 1 1 100.00
sys_loopback 1 1 100.00
uart_loopback 11.270s 9754.672us 1 1 100.00
line_loopback 1 1 100.00
uart_loopback 11.270s 9754.672us 1 1 100.00
rx_noise_filter 0 1 0.00
uart_noise_filter 1.890s 2654.821us 0 1 0.00
rx_start_bit_filter 1 1 100.00
uart_rx_start_bit_filter 2.750s 2640.697us 1 1 100.00
tx_overide 1 1 100.00
uart_tx_ovrd 3.010s 868.083us 1 1 100.00
rx_oversample 1 1 100.00
uart_rx_oversample 5.190s 1568.981us 1 1 100.00
long_b2b_transfer 1 1 100.00
uart_long_xfer_wo_dly 237.640s 311534.175us 1 1 100.00
stress_all 0 1 0.00
uart_stress_all 2.880s 4771.969us 0 1 0.00
alert_test 1 1 100.00
uart_alert_test 0.700s 53.032us 1 1 100.00
intr_test 1 1 100.00
uart_intr_test 0.660s 55.058us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
uart_tl_errors 1.650s 456.979us 1 1 100.00
tl_d_illegal_access 1 1 100.00
uart_tl_errors 1.650s 456.979us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
uart_csr_hw_reset 0.610s 16.554us 1 1 100.00
uart_csr_rw 0.760s 18.729us 1 1 100.00
uart_csr_aliasing 1.070s 31.095us 1 1 100.00
uart_same_csr_outstanding 0.790s 131.715us 1 1 100.00
tl_d_partial_access 4 4 100.00
uart_csr_hw_reset 0.610s 16.554us 1 1 100.00
uart_csr_rw 0.760s 18.729us 1 1 100.00
uart_csr_aliasing 1.070s 31.095us 1 1 100.00
uart_same_csr_outstanding 0.790s 131.715us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
uart_sec_cm 0.920s 42.558us 1 1 100.00
uart_tl_intg_err 0.940s 55.748us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
uart_tl_intg_err 0.940s 55.748us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
uart_stress_all_with_rand_reset 17.510s 1820.880us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (uart_scoreboard.sv:393) [scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (* [*] vs * [*]) check rx_idle fail: rx_en = *, uart_rx_clk_pulses = * 2 test runs
uart_stress_all_with_rand_reset 93492073617278038833552543992384789921367221753830770781309169543970749318668 81
UVM_ERROR @ 250982486 ps: (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
UVM_INFO @ 270376406 ps: (cip_base_vseq__tl_errors.svh:292) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 5/152
UVM_INFO @ 307750106 ps: (cip_base_vseq__tl_errors.svh:292) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 6/152
UVM_INFO @ 319449568 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
uart_stress_all 16850309349782587793298570142443086895207561092049572393209694431063901784355 77
UVM_ERROR @ 2495995297 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 2495995297 ps: (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
UVM_ERROR @ 3605922257 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 3684709547 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR (uart_scoreboard.sv:501) scoreboard [scoreboard] rxlvl mismatch exp: * (+/-1), act: *, clk_pulses: * 1 test run
uart_noise_filter 37124646984170974269703729438729780636853418656148410761429415850134425232168 75
UVM_ERROR @ 2197890351 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 2197973683 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (230 [0xe6] vs 255 [0xff]) reg name: uart_reg_block.rdata
UVM_ERROR @ 2244889599 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
UVM_ERROR @ 2244889599 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0