Simulation Results: adc_ctrl

 
10/08/2026 15:30:36 DVSim: v1.50.1 sha: af43bb2 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 70.64 %
  • code
  • 96.81 %
  • assert
  • 96.60 %
  • func
  • 18.51 %
  • line
  • 99.02 %
  • branch
  • 98.45 %
  • cond
  • 94.71 %
  • toggle
  • 100.00 %
  • FSM
  • 91.89 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
adc_ctrl_smoke 8.790s 5720.020us 1 1 100.00
csr_hw_reset 1 1 100.00
adc_ctrl_csr_hw_reset 1.490s 1101.598us 1 1 100.00
csr_rw 1 1 100.00
adc_ctrl_csr_rw 0.770s 392.823us 1 1 100.00
csr_bit_bash 1 1 100.00
adc_ctrl_csr_bit_bash 25.070s 53230.528us 1 1 100.00
csr_aliasing 1 1 100.00
adc_ctrl_csr_aliasing 2.460s 1053.443us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
adc_ctrl_csr_mem_rw_with_rand_reset 1.100s 457.200us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
adc_ctrl_csr_rw 0.770s 392.823us 1 1 100.00
adc_ctrl_csr_aliasing 2.460s 1053.443us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
filters_polled 1 1 100.00
adc_ctrl_filters_polled 69.830s 55035.229us 1 1 100.00
filters_polled_fixed 1 1 100.00
adc_ctrl_filters_polled_fixed 73.500s 51935.909us 1 1 100.00
filters_interrupt 1 1 100.00
adc_ctrl_filters_interrupt 13.120s 35566.711us 1 1 100.00
filters_interrupt_fixed 1 1 100.00
adc_ctrl_filters_interrupt_fixed 29.000s 19416.771us 1 1 100.00
filters_wakeup 1 1 100.00
adc_ctrl_filters_wakeup 43.130s 73879.666us 1 1 100.00
filters_wakeup_fixed 1 1 100.00
adc_ctrl_filters_wakeup_fixed 23.110s 66441.856us 1 1 100.00
filters_both 1 1 100.00
adc_ctrl_filters_both 64.380s 50431.796us 1 1 100.00
clock_gating 1 1 100.00
adc_ctrl_clock_gating 24.950s 65802.777us 1 1 100.00
poweron_counter 1 1 100.00
adc_ctrl_poweron_counter 6.360s 3846.976us 1 1 100.00
lowpower_counter 1 1 100.00
adc_ctrl_lowpower_counter 13.640s 25738.835us 1 1 100.00
fsm_reset 1 1 100.00
adc_ctrl_fsm_reset 98.190s 123379.512us 1 1 100.00
stress_all 1 1 100.00
adc_ctrl_stress_all 54.620s 37526.665us 1 1 100.00
alert_test 1 1 100.00
adc_ctrl_alert_test 1.170s 438.129us 1 1 100.00
intr_test 1 1 100.00
adc_ctrl_intr_test 1.560s 474.266us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
adc_ctrl_tl_errors 1.300s 465.703us 1 1 100.00
tl_d_illegal_access 1 1 100.00
adc_ctrl_tl_errors 1.300s 465.703us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
adc_ctrl_csr_hw_reset 1.490s 1101.598us 1 1 100.00
adc_ctrl_csr_rw 0.770s 392.823us 1 1 100.00
adc_ctrl_csr_aliasing 2.460s 1053.443us 1 1 100.00
adc_ctrl_same_csr_outstanding 4.190s 2161.914us 1 1 100.00
tl_d_partial_access 4 4 100.00
adc_ctrl_csr_hw_reset 1.490s 1101.598us 1 1 100.00
adc_ctrl_csr_rw 0.770s 392.823us 1 1 100.00
adc_ctrl_csr_aliasing 2.460s 1053.443us 1 1 100.00
adc_ctrl_same_csr_outstanding 4.190s 2161.914us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
adc_ctrl_sec_cm 7.190s 4451.696us 1 1 100.00
adc_ctrl_tl_intg_err 13.470s 8305.284us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
adc_ctrl_tl_intg_err 13.470s 8305.284us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
adc_ctrl_stress_all_with_rand_reset 1.760s 491.845us 1 1 100.00