Simulation Results: aes/unmasked

 
10/08/2026 15:30:36 DVSim: v1.50.1 sha: af43bb2 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 87.53 %
  • code
  • 89.52 %
  • assert
  • 97.73 %
  • func
  • 75.33 %
  • block
  • 90.01 %
  • line
  • 92.39 %
  • branch
  • 81.03 %
  • toggle
  • 97.99 %
  • FSM
  • 86.67 %
Validation stages
V1
100.00%
V2
100.00%
V2S
87.50%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 2.000s 141.568us 1 1 100.00
smoke 1 1 100.00
aes_smoke 3.000s 74.737us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 2.000s 61.809us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 2.000s 72.862us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 4.000s 161.331us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 2.000s 89.311us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 1.000s 65.865us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 2.000s 72.862us 1 1 100.00
aes_csr_aliasing 2.000s 89.311us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 3.000s 74.737us 1 1 100.00
aes_config_error 3.000s 94.853us 1 1 100.00
aes_stress 3.000s 122.104us 1 1 100.00
key_length 3 3 100.00
aes_smoke 3.000s 74.737us 1 1 100.00
aes_config_error 3.000s 94.853us 1 1 100.00
aes_stress 3.000s 122.104us 1 1 100.00
back2back 2 2 100.00
aes_stress 3.000s 122.104us 1 1 100.00
aes_b2b 3.000s 108.402us 1 1 100.00
backpressure 1 1 100.00
aes_stress 3.000s 122.104us 1 1 100.00
multi_message 4 4 100.00
aes_smoke 3.000s 74.737us 1 1 100.00
aes_config_error 3.000s 94.853us 1 1 100.00
aes_stress 3.000s 122.104us 1 1 100.00
aes_alert_reset 3.000s 92.775us 1 1 100.00
failure_test 3 3 100.00
aes_man_cfg_err 2.000s 60.596us 1 1 100.00
aes_config_error 3.000s 94.853us 1 1 100.00
aes_alert_reset 3.000s 92.775us 1 1 100.00
trigger_clear_test 1 1 100.00
aes_clear 3.000s 133.262us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 3.000s 127.241us 1 1 100.00
reset_recovery 1 1 100.00
aes_alert_reset 3.000s 92.775us 1 1 100.00
stress 1 1 100.00
aes_stress 3.000s 122.104us 1 1 100.00
sideload 2 2 100.00
aes_stress 3.000s 122.104us 1 1 100.00
aes_sideload 3.000s 70.443us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 3.000s 686.880us 1 1 100.00
stress_all 1 1 100.00
aes_stress_all 12.000s 257.235us 1 1 100.00
alert_test 1 1 100.00
aes_alert_test 2.000s 62.884us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 1.000s 304.192us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 1.000s 304.192us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 2.000s 61.809us 1 1 100.00
aes_csr_rw 2.000s 72.862us 1 1 100.00
aes_csr_aliasing 2.000s 89.311us 1 1 100.00
aes_same_csr_outstanding 2.000s 74.806us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 2.000s 61.809us 1 1 100.00
aes_csr_rw 2.000s 72.862us 1 1 100.00
aes_csr_aliasing 2.000s 89.311us 1 1 100.00
aes_same_csr_outstanding 2.000s 74.806us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 1 1 100.00
aes_reseed 2.000s 59.567us 1 1 100.00
fault_inject 1 3 33.33
aes_fi 2.000s 118.307us 0 1 0.00
aes_control_fi 60.000s 0.000us 0 1 0.00
aes_cipher_fi 2.000s 55.328us 1 1 100.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 2.000s 75.513us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 2.000s 75.513us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 2.000s 75.513us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 2.000s 75.513us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 3.000s 461.946us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 3.000s 782.633us 1 1 100.00
aes_tl_intg_err 3.000s 574.135us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 3.000s 574.135us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
aes_alert_reset 3.000s 92.775us 1 1 100.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 75.513us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 75.513us 1 1 100.00
sec_cm_main_config_sparse 4 4 100.00
aes_smoke 3.000s 74.737us 1 1 100.00
aes_stress 3.000s 122.104us 1 1 100.00
aes_alert_reset 3.000s 92.775us 1 1 100.00
aes_core_fi 3.000s 79.893us 1 1 100.00
sec_cm_gcm_config_sparse 3 3 100.00
aes_config_error 3.000s 94.853us 1 1 100.00
aes_stress 3.000s 122.104us 1 1 100.00
aes_core_fi 3.000s 79.893us 1 1 100.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 75.513us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 2.000s 109.082us 1 1 100.00
aes_stress 3.000s 122.104us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 3.000s 122.104us 1 1 100.00
aes_sideload 3.000s 70.443us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 2.000s 109.082us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 2.000s 109.082us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 2.000s 109.082us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 2.000s 109.082us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 2.000s 109.082us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 3.000s 122.104us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 3.000s 122.104us 1 1 100.00
sec_cm_main_fsm_sparse 0 1 0.00
aes_fi 2.000s 118.307us 0 1 0.00
sec_cm_main_fsm_redun 2 4 50.00
aes_fi 2.000s 118.307us 0 1 0.00
aes_control_fi 60.000s 0.000us 0 1 0.00
aes_cipher_fi 2.000s 55.328us 1 1 100.00
aes_ctr_fi 2.000s 141.547us 1 1 100.00
sec_cm_cipher_fsm_sparse 0 1 0.00
aes_fi 2.000s 118.307us 0 1 0.00
sec_cm_cipher_fsm_redun 1 3 33.33
aes_fi 2.000s 118.307us 0 1 0.00
aes_control_fi 60.000s 0.000us 0 1 0.00
aes_cipher_fi 2.000s 55.328us 1 1 100.00
sec_cm_cipher_ctr_redun 1 1 100.00
aes_cipher_fi 2.000s 55.328us 1 1 100.00
sec_cm_ctr_fsm_sparse 0 1 0.00
aes_fi 2.000s 118.307us 0 1 0.00
sec_cm_ctr_fsm_redun 1 3 33.33
aes_fi 2.000s 118.307us 0 1 0.00
aes_control_fi 60.000s 0.000us 0 1 0.00
aes_ctr_fi 2.000s 141.547us 1 1 100.00
sec_cm_ghash_fsm_sparse 0 1 0.00
aes_fi 2.000s 118.307us 0 1 0.00
sec_cm_ctrl_sparse 2 4 50.00
aes_fi 2.000s 118.307us 0 1 0.00
aes_control_fi 60.000s 0.000us 0 1 0.00
aes_cipher_fi 2.000s 55.328us 1 1 100.00
aes_ctr_fi 2.000s 141.547us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
aes_alert_reset 3.000s 92.775us 1 1 100.00
sec_cm_main_fsm_local_esc 2 4 50.00
aes_fi 2.000s 118.307us 0 1 0.00
aes_control_fi 60.000s 0.000us 0 1 0.00
aes_cipher_fi 2.000s 55.328us 1 1 100.00
aes_ctr_fi 2.000s 141.547us 1 1 100.00
sec_cm_cipher_fsm_local_esc 2 4 50.00
aes_fi 2.000s 118.307us 0 1 0.00
aes_control_fi 60.000s 0.000us 0 1 0.00
aes_cipher_fi 2.000s 55.328us 1 1 100.00
aes_ctr_fi 2.000s 141.547us 1 1 100.00
sec_cm_ctr_fsm_local_esc 1 3 33.33
aes_fi 2.000s 118.307us 0 1 0.00
aes_control_fi 60.000s 0.000us 0 1 0.00
aes_ctr_fi 2.000s 141.547us 1 1 100.00
sec_cm_ghash_fsm_local_esc 0 1 0.00
aes_fi 2.000s 118.307us 0 1 0.00
sec_cm_data_reg_local_esc 1 3 33.33
aes_fi 2.000s 118.307us 0 1 0.00
aes_control_fi 60.000s 0.000us 0 1 0.00
aes_cipher_fi 2.000s 55.328us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 2.000s 2.083us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (aes_scoreboard.sv:926) scoreboard [scoreboard] 1 test run
aes_fi 61225290840306304770127474291300587466142622403765369675099163883438006367408 7807
----| NO FAILURES BUT NUMBER OF EXPECTED MESSAGES DOES NOT MATCH ACTUAL
----| Expected: 5
----| Seen: 3
----| Expected corrupted: 0
Job timed out after * minutes 1 test run
aes_control_fi 89878958338920306685136454407954081578366008890478156724637810882203119363751 None
UVM_FATAL (aes_base_vseq.sv:87) [aes_stress_all_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) 1 test run
aes_stress_all_with_rand_reset 58062924792523617842424033315796916489988523558275752201996844667065554034298 109
UVM_INFO @ 2083324 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---