Simulation Results: chip

 
10/08/2026 15:30:36 DVSim: v1.50.1 sha: af43bb2 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 73.15 %
  • code
  • 81.65 %
  • assert
  • 97.37 %
  • func
  • 40.43 %
  • line
  • 94.44 %
  • branch
  • 93.82 %
  • cond
  • 89.17 %
  • toggle
  • 73.68 %
  • FSM
  • 57.14 %
Validation stages
V1
94.44%
V2
89.53%
V2S
100.00%
V3
65.38%
unmapped
63.64%
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_example_tests 4 4 100.00
chip_sw_example_flash 154.430s 2961.916us 1 1 100.00
chip_sw_example_rom 103.850s 2148.010us 1 1 100.00
chip_sw_example_manufacturer 202.580s 3649.106us 1 1 100.00
chip_sw_example_concurrency 197.790s 4164.050us 1 1 100.00
csr_hw_reset 1 1 100.00
chip_csr_hw_reset 254.230s 6649.178us 1 1 100.00
csr_rw 1 1 100.00
chip_csr_rw 304.040s 4636.198us 1 1 100.00
csr_bit_bash 1 1 100.00
chip_csr_bit_bash 656.630s 8476.389us 1 1 100.00
csr_aliasing 1 1 100.00
chip_csr_aliasing 5172.290s 35724.670us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
chip_csr_mem_rw_with_rand_reset 79.040s 2855.754us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
chip_csr_aliasing 5172.290s 35724.670us 1 1 100.00
chip_csr_rw 304.040s 4636.198us 1 1 100.00
xbar_smoke 1 1 100.00
xbar_smoke 6.670s 195.148us 1 1 100.00
chip_sw_gpio_out 1 1 100.00
chip_sw_gpio 310.860s 4621.172us 1 1 100.00
chip_sw_gpio_in 1 1 100.00
chip_sw_gpio 310.860s 4621.172us 1 1 100.00
chip_sw_gpio_irq 1 1 100.00
chip_sw_gpio 310.860s 4621.172us 1 1 100.00
chip_sw_uart_tx_rx 1 1 100.00
chip_sw_uart_tx_rx 388.640s 5257.082us 1 1 100.00
chip_sw_uart_rx_overflow 4 4 100.00
chip_sw_uart_tx_rx 388.640s 5257.082us 1 1 100.00
chip_sw_uart_tx_rx_idx1 424.440s 5528.214us 1 1 100.00
chip_sw_uart_tx_rx_idx2 444.080s 4686.928us 1 1 100.00
chip_sw_uart_tx_rx_idx3 370.170s 4835.212us 1 1 100.00
chip_sw_uart_baud_rate 1 1 100.00
chip_sw_uart_rand_baudrate 417.320s 4189.264us 1 1 100.00
chip_sw_uart_tx_rx_alt_clk_freq 2 2 100.00
chip_sw_uart_tx_rx_alt_clk_freq 1174.040s 9381.721us 1 1 100.00
chip_sw_uart_tx_rx_alt_clk_freq_low_speed 341.480s 5660.369us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_pin_mux 1 1 100.00
chip_padctrl_attributes 292.130s 6372.106us 1 1 100.00
chip_padctrl_attributes 1 1 100.00
chip_padctrl_attributes 292.130s 6372.106us 1 1 100.00
chip_sw_sleep_pin_mio_dio_val 1 1 100.00
chip_sw_sleep_pin_mio_dio_val 224.730s 3861.288us 1 1 100.00
chip_sw_sleep_pin_wake 1 1 100.00
chip_sw_sleep_pin_wake 261.590s 3774.051us 1 1 100.00
chip_sw_sleep_pin_retention 1 1 100.00
chip_sw_sleep_pin_retention 273.560s 4583.594us 1 1 100.00
chip_sw_tap_strap_sampling 4 4 100.00
chip_tap_straps_dev 109.460s 3155.934us 1 1 100.00
chip_tap_straps_testunlock0 136.560s 3719.251us 1 1 100.00
chip_tap_straps_rma 685.190s 9892.180us 1 1 100.00
chip_tap_straps_prod 957.520s 12677.363us 1 1 100.00
chip_sw_data_integrity 1 1 100.00
chip_sw_data_integrity_escalation 489.370s 6163.970us 1 1 100.00
chip_sw_instruction_integrity 1 1 100.00
chip_sw_data_integrity_escalation 489.370s 6163.970us 1 1 100.00
chip_sw_ast_clk_outputs 1 1 100.00
chip_sw_ast_clk_outputs 709.250s 8724.876us 1 1 100.00
chip_sw_ast_clk_rst_inputs 0 1 0.00
chip_sw_ast_clk_rst_inputs 1655.130s 15698.275us 0 1 0.00
chip_sw_ast_sys_clk_jitter 10 10 100.00
chip_sw_flash_ctrl_ops_jitter_en 371.780s 4124.428us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en 596.870s 5808.578us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 4359.970s 19217.934us 1 1 100.00
chip_sw_aes_enc_jitter_en 256.100s 3980.664us 1 1 100.00
chip_sw_edn_entropy_reqs_jitter 769.680s 7148.275us 1 1 100.00
chip_sw_hmac_enc_jitter_en 185.580s 3438.843us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en 891.600s 8668.082us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en 270.820s 4039.737us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 503.890s 6877.697us 1 1 100.00
chip_sw_clkmgr_jitter 192.880s 4200.739us 1 1 100.00
chip_sw_ast_usb_clk_calib 1 1 100.00
chip_sw_usb_ast_clk_calib 271.850s 3698.876us 1 1 100.00
chip_sw_sensor_ctrl_ast_alerts 2 2 100.00
chip_sw_sensor_ctrl_alert 849.300s 8620.425us 1 1 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 296.540s 5010.064us 1 1 100.00
chip_sw_sensor_ctrl_ast_status 1 1 100.00
chip_sw_sensor_ctrl_status 184.050s 3670.243us 1 1 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 1 1 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 296.540s 5010.064us 1 1 100.00
chip_sw_smoketest 17 17 100.00
chip_sw_flash_scrambling_smoketest 183.250s 3105.215us 1 1 100.00
chip_sw_aes_smoketest 221.100s 3565.384us 1 1 100.00
chip_sw_aon_timer_smoketest 206.120s 3329.959us 1 1 100.00
chip_sw_clkmgr_smoketest 224.000s 2990.304us 1 1 100.00
chip_sw_csrng_smoketest 161.950s 3999.440us 1 1 100.00
chip_sw_entropy_src_smoketest 943.980s 6970.196us 1 1 100.00
chip_sw_gpio_smoketest 274.240s 3999.069us 1 1 100.00
chip_sw_hmac_smoketest 193.560s 4118.185us 1 1 100.00
chip_sw_kmac_smoketest 220.470s 2886.272us 1 1 100.00
chip_sw_otbn_smoketest 1627.030s 10299.367us 1 1 100.00
chip_sw_pwrmgr_smoketest 366.710s 6807.484us 1 1 100.00
chip_sw_pwrmgr_usbdev_smoketest 445.660s 7462.065us 1 1 100.00
chip_sw_rv_plic_smoketest 232.320s 3901.021us 1 1 100.00
chip_sw_rv_timer_smoketest 168.190s 3673.790us 1 1 100.00
chip_sw_rstmgr_smoketest 169.480s 3573.267us 1 1 100.00
chip_sw_sram_ctrl_smoketest 171.510s 4076.185us 1 1 100.00
chip_sw_uart_smoketest 220.630s 3636.709us 1 1 100.00
chip_sw_otp_smoketest 1 1 100.00
chip_sw_otp_ctrl_smoketest 246.480s 3854.455us 1 1 100.00
chip_sw_rom_functests 0 1 0.00
rom_keymgr_functest 429.060s 6800.716us 0 1 0.00
chip_sw_boot 1 1 100.00
chip_sw_uart_tx_rx_bootstrap 9496.320s 61350.600us 1 1 100.00
chip_sw_secure_boot 1 1 100.00
rom_e2e_smoke 3471.720s 17051.267us 1 1 100.00
chip_sw_rom_raw_unlock 1 1 100.00
rom_raw_unlock 187.090s 5499.150us 1 1 100.00
chip_sw_power_idle_load 0 1 0.00
chip_sw_power_idle_load 1340.140s 15303.342us 0 1 0.00
chip_sw_power_sleep_load 0 1 0.00
chip_sw_power_sleep_load 1124.220s 15673.143us 0 1 0.00
chip_sw_exit_test_unlocked_bootstrap 1 1 100.00
chip_sw_exit_test_unlocked_bootstrap 8289.090s 55781.572us 1 1 100.00
chip_sw_inject_scramble_seed 1 1 100.00
chip_sw_inject_scramble_seed 9551.470s 59406.734us 1 1 100.00
tl_d_oob_addr_access 0 1 0.00
chip_tl_errors 69.320s 2357.429us 0 1 0.00
tl_d_illegal_access 0 1 0.00
chip_tl_errors 69.320s 2357.429us 0 1 0.00
tl_d_outstanding_access 4 4 100.00
chip_csr_aliasing 5172.290s 35724.670us 1 1 100.00
chip_same_csr_outstanding 1590.500s 14271.123us 1 1 100.00
chip_csr_hw_reset 254.230s 6649.178us 1 1 100.00
chip_csr_rw 304.040s 4636.198us 1 1 100.00
tl_d_partial_access 4 4 100.00
chip_csr_aliasing 5172.290s 35724.670us 1 1 100.00
chip_same_csr_outstanding 1590.500s 14271.123us 1 1 100.00
chip_csr_hw_reset 254.230s 6649.178us 1 1 100.00
chip_csr_rw 304.040s 4636.198us 1 1 100.00
xbar_base_random_sequence 1 1 100.00
xbar_random 13.360s 463.178us 1 1 100.00
xbar_random_delay 6 6 100.00
xbar_smoke_zero_delays 4.720s 44.387us 1 1 100.00
xbar_smoke_large_delays 44.920s 7413.977us 1 1 100.00
xbar_smoke_slow_rsp 58.110s 6151.313us 1 1 100.00
xbar_random_zero_delays 30.510s 499.466us 1 1 100.00
xbar_random_large_delays 64.000s 10051.717us 1 1 100.00
xbar_random_slow_rsp 72.830s 6456.701us 1 1 100.00
xbar_unmapped_address 2 2 100.00
xbar_unmapped_addr 11.610s 109.861us 1 1 100.00
xbar_error_and_unmapped_addr 7.170s 67.738us 1 1 100.00
xbar_error_cases 2 2 100.00
xbar_error_random 40.170s 1451.005us 1 1 100.00
xbar_error_and_unmapped_addr 7.170s 67.738us 1 1 100.00
xbar_all_access_same_device 2 2 100.00
xbar_access_same_device 56.040s 1904.581us 1 1 100.00
xbar_access_same_device_slow_rsp 413.990s 43578.769us 1 1 100.00
xbar_all_hosts_use_same_source_id 1 1 100.00
xbar_same_source 12.530s 514.612us 1 1 100.00
xbar_stress_all 2 2 100.00
xbar_stress_all 354.680s 14161.889us 1 1 100.00
xbar_stress_all_with_error 114.440s 2007.393us 1 1 100.00
xbar_stress_with_reset 2 2 100.00
xbar_stress_all_with_rand_reset 4.680s 7.162us 1 1 100.00
xbar_stress_all_with_reset_error 13.870s 49.583us 1 1 100.00
rom_e2e_smoke 1 1 100.00
rom_e2e_smoke 3471.720s 17051.267us 1 1 100.00
rom_e2e_shutdown_output 1 1 100.00
rom_e2e_shutdown_output 3056.500s 36059.752us 1 1 100.00
rom_e2e_shutdown_exception_c 1 1 100.00
rom_e2e_shutdown_exception_c 3147.480s 14786.631us 1 1 100.00
rom_e2e_boot_policy_valid 15 15 100.00
rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 2560.370s 11757.816us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_good_dev 3445.710s 16780.805us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_good_prod 3450.410s 15628.341us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_good_prod_end 3492.770s 17084.690us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_good_rma 3425.360s 15517.501us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 2741.370s 12661.947us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_bad_dev 3490.350s 19268.138us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_bad_prod 3379.920s 16792.506us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_bad_prod_end 3353.850s 16186.908us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_bad_rma 3466.220s 15697.055us 1 1 100.00
rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 4998.240s 18213.346us 1 1 100.00
rom_e2e_boot_policy_valid_a_bad_b_good_dev 6230.750s 28508.023us 1 1 100.00
rom_e2e_boot_policy_valid_a_bad_b_good_prod 6328.430s 24607.739us 1 1 100.00
rom_e2e_boot_policy_valid_a_bad_b_good_prod_end 6175.060s 25733.432us 1 1 100.00
rom_e2e_boot_policy_valid_a_bad_b_good_rma 5838.390s 24160.094us 1 1 100.00
rom_e2e_sigverify_always 15 15 100.00
rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 4864.890s 22269.385us 1 1 100.00
rom_e2e_sigverify_always_a_bad_b_bad_dev 6172.920s 23247.082us 1 1 100.00
rom_e2e_sigverify_always_a_bad_b_bad_prod 6420.080s 30558.448us 1 1 100.00
rom_e2e_sigverify_always_a_bad_b_bad_prod_end 6195.320s 24021.376us 1 1 100.00
rom_e2e_sigverify_always_a_bad_b_bad_rma 5813.490s 25204.244us 1 1 100.00
rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 2439.380s 13710.548us 1 1 100.00
rom_e2e_sigverify_always_a_bad_b_nothing_dev 3255.220s 15202.941us 1 1 100.00
rom_e2e_sigverify_always_a_bad_b_nothing_prod 3125.960s 14794.516us 1 1 100.00
rom_e2e_sigverify_always_a_bad_b_nothing_prod_end 3461.840s 16253.503us 1 1 100.00
rom_e2e_sigverify_always_a_bad_b_nothing_rma 2966.220s 14919.663us 1 1 100.00
rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 2556.220s 12218.086us 1 1 100.00
rom_e2e_sigverify_always_a_nothing_b_bad_dev 3280.100s 15415.356us 1 1 100.00
rom_e2e_sigverify_always_a_nothing_b_bad_prod 3395.470s 15707.642us 1 1 100.00
rom_e2e_sigverify_always_a_nothing_b_bad_prod_end 3220.960s 15210.484us 1 1 100.00
rom_e2e_sigverify_always_a_nothing_b_bad_rma 3110.190s 14366.293us 1 1 100.00
rom_e2e_asm_init 5 5 100.00
rom_e2e_asm_init_test_unlocked0 2560.330s 11976.273us 1 1 100.00
rom_e2e_asm_init_dev 3578.930s 16355.193us 1 1 100.00
rom_e2e_asm_init_prod 3596.160s 18707.966us 1 1 100.00
rom_e2e_asm_init_prod_end 3300.460s 15894.119us 1 1 100.00
rom_e2e_asm_init_rma 3288.090s 15821.123us 1 1 100.00
rom_e2e_keymgr_init 2 3 66.67
rom_e2e_keymgr_init_rom_ext_meas 6880.360s 29364.471us 1 1 100.00
rom_e2e_keymgr_init_rom_ext_no_meas 6933.740s 35500.779us 1 1 100.00
rom_e2e_keymgr_init_rom_ext_invalid_meas 3864.690s 23902.689us 0 1 0.00
rom_e2e_static_critical 1 1 100.00
rom_e2e_static_critical 3395.980s 17404.182us 1 1 100.00
chip_sw_adc_ctrl_debug_cable_irq 0 1 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 3081.390s 35689.132us 0 1 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 0 1 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 3081.390s 35689.132us 0 1 0.00
chip_sw_aes_enc 2 2 100.00
chip_sw_aes_enc 264.010s 3166.720us 1 1 100.00
chip_sw_aes_enc_jitter_en 256.100s 3980.664us 1 1 100.00
chip_sw_aes_entropy 1 1 100.00
chip_sw_aes_entropy 178.300s 3079.610us 1 1 100.00
chip_sw_aes_idle 1 1 100.00
chip_sw_aes_idle 233.960s 3652.909us 1 1 100.00
chip_sw_aes_sideload 1 1 100.00
chip_sw_keymgr_sideload_aes 1718.170s 13421.997us 1 1 100.00
chip_sw_alert_handler_alerts 0 1 0.00
chip_sw_alert_test 247.230s 3468.145us 0 1 0.00
chip_sw_alert_handler_escalations 1 1 100.00
chip_sw_alert_handler_escalation 447.750s 6245.904us 1 1 100.00
chip_sw_all_escalation_resets 1 1 100.00
chip_sw_all_escalation_resets 407.910s 6410.705us 1 1 100.00
chip_sw_alert_handler_irqs 3 3 100.00
chip_plic_all_irqs_0 592.600s 5875.999us 1 1 100.00
chip_plic_all_irqs_10 359.380s 4938.063us 1 1 100.00
chip_plic_all_irqs_20 433.670s 4614.744us 1 1 100.00
chip_sw_alert_handler_entropy 1 1 100.00
chip_sw_alert_handler_entropy 217.410s 3760.194us 1 1 100.00
chip_sw_alert_handler_crashdump 1 1 100.00
chip_sw_rstmgr_alert_info 1518.080s 18152.257us 1 1 100.00
chip_sw_alert_handler_ping_timeout 1 1 100.00
chip_sw_alert_handler_ping_timeout 207.310s 3846.602us 1 1 100.00
chip_sw_alert_handler_lpg_sleep_mode_alerts 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_alerts 165.070s 3164.111us 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_pings 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_pings 14400.151s 0.000us 0 1 0.00
chip_sw_alert_handler_lpg_clock_off 1 1 100.00
chip_sw_alert_handler_lpg_clkoff 1419.540s 9968.837us 1 1 100.00
chip_sw_alert_handler_lpg_reset_toggle 1 1 100.00
chip_sw_alert_handler_lpg_reset_toggle 1356.660s 8897.312us 1 1 100.00
chip_sw_alert_handler_ping_ok 1 1 100.00
chip_sw_alert_handler_ping_ok 1017.700s 8368.090us 1 1 100.00
chip_sw_alert_handler_reverse_ping_in_deep_sleep 1 1 100.00
chip_sw_alert_handler_reverse_ping_in_deep_sleep 9508.810s 257645.683us 1 1 100.00
chip_sw_aon_timer_wakeup_irq 1 1 100.00
chip_sw_aon_timer_irq 283.880s 5254.211us 1 1 100.00
chip_sw_aon_timer_sleep_wakeup 1 1 100.00
chip_sw_pwrmgr_smoketest 366.710s 6807.484us 1 1 100.00
chip_sw_aon_timer_wdog_bark_irq 1 1 100.00
chip_sw_aon_timer_irq 283.880s 5254.211us 1 1 100.00
chip_sw_aon_timer_wdog_bite_reset 0 1 0.00
chip_sw_aon_timer_wdog_bite_reset 575.150s 8515.250us 0 1 0.00
chip_sw_aon_timer_sleep_wdog_bite_reset 0 1 0.00
chip_sw_aon_timer_wdog_bite_reset 575.150s 8515.250us 0 1 0.00
chip_sw_aon_timer_sleep_wdog_sleep_pause 1 1 100.00
chip_sw_aon_timer_sleep_wdog_sleep_pause 458.510s 8604.429us 1 1 100.00
chip_sw_aon_timer_wdog_lc_escalate 1 1 100.00
chip_sw_aon_timer_wdog_lc_escalate 428.240s 5507.832us 1 1 100.00
chip_sw_clkmgr_idle_trans 4 4 100.00
chip_sw_otbn_randomness 715.610s 6126.273us 1 1 100.00
chip_sw_aes_idle 233.960s 3652.909us 1 1 100.00
chip_sw_hmac_enc_idle 240.300s 4486.031us 1 1 100.00
chip_sw_kmac_idle 180.110s 3244.406us 1 1 100.00
chip_sw_clkmgr_off_trans 4 4 100.00
chip_sw_clkmgr_off_aes_trans 268.940s 4629.872us 1 1 100.00
chip_sw_clkmgr_off_hmac_trans 403.020s 6003.238us 1 1 100.00
chip_sw_clkmgr_off_kmac_trans 422.430s 5389.609us 1 1 100.00
chip_sw_clkmgr_off_otbn_trans 395.870s 5084.579us 1 1 100.00
chip_sw_clkmgr_off_peri 1 1 100.00
chip_sw_clkmgr_off_peri 962.200s 13783.588us 1 1 100.00
chip_sw_clkmgr_div 7 7 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 453.660s 4266.774us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 454.800s 5106.349us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 528.910s 5655.919us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 471.920s 5345.460us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_rma 471.840s 4873.599us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_rma 422.790s 4547.297us 1 1 100.00
chip_sw_ast_clk_outputs 709.250s 8724.876us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_lc 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_lc 687.410s 13737.715us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw 2 2 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 528.910s 5655.919us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 471.920s 5345.460us 1 1 100.00
chip_sw_clkmgr_jitter 10 10 100.00
chip_sw_flash_ctrl_ops_jitter_en 371.780s 4124.428us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en 596.870s 5808.578us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 4359.970s 19217.934us 1 1 100.00
chip_sw_aes_enc_jitter_en 256.100s 3980.664us 1 1 100.00
chip_sw_edn_entropy_reqs_jitter 769.680s 7148.275us 1 1 100.00
chip_sw_hmac_enc_jitter_en 185.580s 3438.843us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en 891.600s 8668.082us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en 270.820s 4039.737us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 503.890s 6877.697us 1 1 100.00
chip_sw_clkmgr_jitter 192.880s 4200.739us 1 1 100.00
chip_sw_clkmgr_extended_range 11 11 100.00
chip_sw_clkmgr_jitter_reduced_freq 178.980s 3060.371us 1 1 100.00
chip_sw_flash_ctrl_ops_jitter_en_reduced_freq 447.820s 4791.343us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en_reduced_freq 696.720s 8177.284us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq 4275.370s 25297.972us 1 1 100.00
chip_sw_aes_enc_jitter_en_reduced_freq 269.390s 3956.425us 1 1 100.00
chip_sw_hmac_enc_jitter_en_reduced_freq 214.770s 4137.495us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en_reduced_freq 707.910s 7841.799us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en_reduced_freq 267.200s 4929.728us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq 416.070s 5078.142us 1 1 100.00
chip_sw_flash_init_reduced_freq 1555.130s 32292.630us 1 1 100.00
chip_sw_csrng_edn_concurrency_reduced_freq 1802.430s 14002.530us 1 1 100.00
chip_sw_clkmgr_deep_sleep_frequency 1 1 100.00
chip_sw_ast_clk_outputs 709.250s 8724.876us 1 1 100.00
chip_sw_clkmgr_sleep_frequency 1 1 100.00
chip_sw_clkmgr_sleep_frequency 413.890s 4695.981us 1 1 100.00
chip_sw_clkmgr_reset_frequency 1 1 100.00
chip_sw_clkmgr_reset_frequency 290.690s 3646.390us 1 1 100.00
chip_sw_clkmgr_escalation_reset 1 1 100.00
chip_sw_all_escalation_resets 407.910s 6410.705us 1 1 100.00
chip_sw_clkmgr_alert_handler_clock_enables 1 1 100.00
chip_sw_alert_handler_lpg_clkoff 1419.540s 9968.837us 1 1 100.00
chip_sw_csrng_edn_cmd 1 1 100.00
chip_sw_entropy_src_csrng 2428.090s 24373.164us 1 1 100.00
chip_sw_csrng_fuse_en_sw_app_read 1 1 100.00
chip_sw_csrng_fuse_en_sw_app_read_test 336.770s 5288.991us 1 1 100.00
chip_sw_csrng_lc_hw_debug_en 1 1 100.00
chip_sw_csrng_lc_hw_debug_en_test 509.410s 7291.952us 1 1 100.00
chip_sw_csrng_known_answer_tests 1 1 100.00
chip_sw_csrng_kat_test 217.190s 4107.642us 1 1 100.00
chip_sw_edn_entropy_reqs 3 3 100.00
chip_sw_csrng_edn_concurrency 2836.900s 15552.154us 1 1 100.00
chip_sw_entropy_src_ast_rng_req 238.650s 3449.287us 1 1 100.00
chip_sw_edn_entropy_reqs 719.660s 6737.446us 1 1 100.00
chip_sw_entropy_src_ast_rng_req 1 1 100.00
chip_sw_entropy_src_ast_rng_req 238.650s 3449.287us 1 1 100.00
chip_sw_entropy_src_csrng 1 1 100.00
chip_sw_entropy_src_csrng 2428.090s 24373.164us 1 1 100.00
chip_sw_entropy_src_known_answer_tests 1 1 100.00
chip_sw_entropy_src_kat_test 187.720s 3244.945us 1 1 100.00
chip_sw_flash_init 1 1 100.00
chip_sw_flash_init 1599.420s 32261.717us 1 1 100.00
chip_sw_flash_host_access 2 2 100.00
chip_sw_flash_ctrl_access 672.480s 5310.352us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en 596.870s 5808.578us 1 1 100.00
chip_sw_flash_ctrl_ops 2 2 100.00
chip_sw_flash_ctrl_ops 364.290s 4433.838us 1 1 100.00
chip_sw_flash_ctrl_ops_jitter_en 371.780s 4124.428us 1 1 100.00
chip_sw_flash_rma_unlocked 1 1 100.00
chip_sw_flash_rma_unlocked 4305.060s 43518.027us 1 1 100.00
chip_sw_flash_scramble 1 1 100.00
chip_sw_flash_init 1599.420s 32261.717us 1 1 100.00
chip_sw_flash_idle_low_power 1 1 100.00
chip_sw_flash_ctrl_idle_low_power 259.100s 4718.149us 1 1 100.00
chip_sw_flash_keymgr_seeds 1 1 100.00
chip_sw_keymgr_key_derivation 1421.120s 10777.093us 1 1 100.00
chip_sw_flash_lc_creator_seed_sw_rw_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 261.180s 4060.837us 0 1 0.00
chip_sw_flash_creator_seed_wipe_on_rma 1 1 100.00
chip_sw_flash_rma_unlocked 4305.060s 43518.027us 1 1 100.00
chip_sw_flash_lc_owner_seed_sw_rw_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 261.180s 4060.837us 0 1 0.00
chip_sw_flash_lc_iso_part_sw_rd_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 261.180s 4060.837us 0 1 0.00
chip_sw_flash_lc_iso_part_sw_wr_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 261.180s 4060.837us 0 1 0.00
chip_sw_flash_lc_seed_hw_rd_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 261.180s 4060.837us 0 1 0.00
chip_sw_flash_lc_escalate_en 1 1 100.00
chip_sw_all_escalation_resets 407.910s 6410.705us 1 1 100.00
chip_sw_flash_prim_tl_access 1 1 100.00
chip_prim_tl_access 144.200s 4813.087us 1 1 100.00
chip_sw_flash_ctrl_clock_freqs 1 1 100.00
chip_sw_flash_ctrl_clock_freqs 665.320s 6126.826us 1 1 100.00
chip_sw_flash_ctrl_escalation_reset 1 1 100.00
chip_sw_flash_crash_alert 463.720s 5916.526us 1 1 100.00
chip_sw_flash_ctrl_write_clear 1 1 100.00
chip_sw_flash_crash_alert 463.720s 5916.526us 1 1 100.00
chip_sw_hmac_enc 2 2 100.00
chip_sw_hmac_enc 202.590s 4240.683us 1 1 100.00
chip_sw_hmac_enc_jitter_en 185.580s 3438.843us 1 1 100.00
chip_sw_hmac_idle 1 1 100.00
chip_sw_hmac_enc_idle 240.300s 4486.031us 1 1 100.00
chip_sw_hmac_all_configurations 1 1 100.00
chip_sw_hmac_oneshot 878.310s 6602.395us 1 1 100.00
chip_sw_hmac_multistream_mode 0 1 0.00
chip_sw_hmac_multistream 1879.780s 12018.672us 0 1 0.00
chip_sw_i2c_host_tx_rx 3 3 100.00
chip_sw_i2c_host_tx_rx 387.210s 4927.611us 1 1 100.00
chip_sw_i2c_host_tx_rx_idx1 457.760s 5882.028us 1 1 100.00
chip_sw_i2c_host_tx_rx_idx2 383.680s 4712.066us 1 1 100.00
chip_sw_i2c_device_tx_rx 1 1 100.00
chip_sw_i2c_device_tx_rx 361.870s 4949.006us 1 1 100.00
chip_sw_keymgr_key_derivation 2 2 100.00
chip_sw_keymgr_key_derivation 1421.120s 10777.093us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en 891.600s 8668.082us 1 1 100.00
chip_sw_keymgr_sideload_kmac 1 1 100.00
chip_sw_keymgr_sideload_kmac 1995.380s 13588.162us 1 1 100.00
chip_sw_keymgr_sideload_aes 1 1 100.00
chip_sw_keymgr_sideload_aes 1718.170s 13421.997us 1 1 100.00
chip_sw_keymgr_sideload_otbn 0 1 0.00
chip_sw_keymgr_sideload_otbn 4096.170s 20026.909us 0 1 0.00
chip_sw_kmac_enc 3 3 100.00
chip_sw_kmac_mode_cshake 248.390s 3905.165us 1 1 100.00
chip_sw_kmac_mode_kmac 254.130s 3651.551us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en 270.820s 4039.737us 1 1 100.00
chip_sw_kmac_app_keymgr 1 1 100.00
chip_sw_keymgr_key_derivation 1421.120s 10777.093us 1 1 100.00
chip_sw_kmac_app_lc 1 1 100.00
chip_sw_lc_ctrl_transition 348.020s 5410.726us 1 1 100.00
chip_sw_kmac_app_rom 1 1 100.00
chip_sw_kmac_app_rom 279.460s 3890.318us 1 1 100.00
chip_sw_kmac_entropy 1 1 100.00
chip_sw_kmac_entropy 1026.840s 7388.919us 1 1 100.00
chip_sw_kmac_idle 1 1 100.00
chip_sw_kmac_idle 180.110s 3244.406us 1 1 100.00
chip_sw_lc_ctrl_alert_handler_escalation 1 1 100.00
chip_sw_alert_handler_escalation 447.750s 6245.904us 1 1 100.00
chip_sw_lc_ctrl_jtag_access 3 3 100.00
chip_tap_straps_dev 109.460s 3155.934us 1 1 100.00
chip_tap_straps_rma 685.190s 9892.180us 1 1 100.00
chip_tap_straps_prod 957.520s 12677.363us 1 1 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 1 1 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 202.610s 3473.047us 1 1 100.00
chip_sw_lc_ctrl_init 1 1 100.00
chip_sw_lc_ctrl_transition 348.020s 5410.726us 1 1 100.00
chip_sw_lc_ctrl_transitions 1 1 100.00
chip_sw_lc_ctrl_transition 348.020s 5410.726us 1 1 100.00
chip_sw_lc_ctrl_kmac_req 1 1 100.00
chip_sw_lc_ctrl_transition 348.020s 5410.726us 1 1 100.00
chip_sw_lc_ctrl_key_div 1 1 100.00
chip_sw_keymgr_key_derivation_prod 1849.700s 13143.530us 1 1 100.00
chip_sw_lc_ctrl_broadcast 19 22 86.36
chip_sw_flash_ctrl_lc_rw_en 261.180s 4060.837us 0 1 0.00
chip_sw_flash_rma_unlocked 4305.060s 43518.027us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_test_unlocked0 244.200s 3127.043us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_dev 583.480s 8962.291us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_prod 731.900s 9745.621us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_rma 648.420s 9857.093us 0 1 0.00
chip_sw_lc_ctrl_transition 348.020s 5410.726us 1 1 100.00
chip_sw_keymgr_key_derivation 1421.120s 10777.093us 1 1 100.00
chip_sw_rom_ctrl_integrity_check 457.150s 11135.704us 1 1 100.00
chip_sw_sram_ctrl_execution_main 663.090s 10790.298us 1 1 100.00
chip_prim_tl_access 144.200s 4813.087us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_lc 687.410s 13737.715us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 453.660s 4266.774us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 454.800s 5106.349us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 528.910s 5655.919us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 471.920s 5345.460us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_rma 471.840s 4873.599us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_rma 422.790s 4547.297us 1 1 100.00
chip_tap_straps_dev 109.460s 3155.934us 1 1 100.00
chip_tap_straps_rma 685.190s 9892.180us 1 1 100.00
chip_tap_straps_prod 957.520s 12677.363us 1 1 100.00
chip_rv_dm_lc_disabled 127.900s 4762.488us 0 1 0.00
chip_lc_scrap 4 4 100.00
chip_sw_lc_ctrl_rma_to_scrap 212.870s 4638.681us 1 1 100.00
chip_sw_lc_ctrl_raw_to_scrap 111.290s 4148.184us 1 1 100.00
chip_sw_lc_ctrl_test_locked0_to_scrap 111.950s 3645.953us 1 1 100.00
chip_sw_lc_ctrl_rand_to_scrap 142.910s 4489.093us 1 1 100.00
chip_lc_test_locked 1 2 50.00
chip_sw_lc_walkthrough_testunlocks 1844.310s 28276.572us 1 1 100.00
chip_rv_dm_lc_disabled 127.900s 4762.488us 0 1 0.00
chip_sw_lc_walkthrough 2 5 40.00
chip_sw_lc_walkthrough_dev 902.810s 10652.332us 0 1 0.00
chip_sw_lc_walkthrough_prod 813.260s 13057.372us 0 1 0.00
chip_sw_lc_walkthrough_prodend 904.450s 11394.308us 1 1 100.00
chip_sw_lc_walkthrough_rma 452.220s 8870.628us 0 1 0.00
chip_sw_lc_walkthrough_testunlocks 1844.310s 28276.572us 1 1 100.00
chip_sw_lc_ctrl_volatile_raw_unlock 2 3 66.67
chip_sw_lc_ctrl_volatile_raw_unlock 112.640s 2999.545us 1 1 100.00
chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz 1106.650s 26471.112us 0 1 0.00
rom_volatile_raw_unlock 66.830s 2230.210us 1 1 100.00
chip_sw_otbn_op 2 2 100.00
chip_sw_otbn_ecdsa_op_irq 4253.020s 18645.151us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 4359.970s 19217.934us 1 1 100.00
chip_sw_otbn_rnd_entropy 1 1 100.00
chip_sw_otbn_randomness 715.610s 6126.273us 1 1 100.00
chip_sw_otbn_urnd_entropy 1 1 100.00
chip_sw_otbn_randomness 715.610s 6126.273us 1 1 100.00
chip_sw_otbn_idle 1 1 100.00
chip_sw_otbn_randomness 715.610s 6126.273us 1 1 100.00
chip_sw_otbn_mem_scramble 1 1 100.00
chip_sw_otbn_mem_scramble 350.730s 3465.753us 1 1 100.00
chip_otp_ctrl_init 1 1 100.00
chip_sw_lc_ctrl_transition 348.020s 5410.726us 1 1 100.00
chip_sw_otp_ctrl_keys 5 5 100.00
chip_sw_flash_init 1599.420s 32261.717us 1 1 100.00
chip_sw_otbn_mem_scramble 350.730s 3465.753us 1 1 100.00
chip_sw_keymgr_key_derivation 1421.120s 10777.093us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access 502.970s 6795.459us 1 1 100.00
chip_sw_rv_core_ibex_icache_invalidate 161.300s 3123.969us 1 1 100.00
chip_sw_otp_ctrl_entropy 5 5 100.00
chip_sw_flash_init 1599.420s 32261.717us 1 1 100.00
chip_sw_otbn_mem_scramble 350.730s 3465.753us 1 1 100.00
chip_sw_keymgr_key_derivation 1421.120s 10777.093us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access 502.970s 6795.459us 1 1 100.00
chip_sw_rv_core_ibex_icache_invalidate 161.300s 3123.969us 1 1 100.00
chip_sw_otp_ctrl_program 1 1 100.00
chip_sw_lc_ctrl_transition 348.020s 5410.726us 1 1 100.00
chip_sw_otp_ctrl_program_error 1 1 100.00
chip_sw_lc_ctrl_program_error 463.520s 6463.753us 1 1 100.00
chip_sw_otp_ctrl_hw_cfg0 1 1 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 202.610s 3473.047us 1 1 100.00
chip_sw_otp_ctrl_lc_signals 5 6 83.33
chip_sw_otp_ctrl_lc_signals_test_unlocked0 244.200s 3127.043us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_dev 583.480s 8962.291us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_prod 731.900s 9745.621us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_rma 648.420s 9857.093us 0 1 0.00
chip_sw_lc_ctrl_transition 348.020s 5410.726us 1 1 100.00
chip_prim_tl_access 144.200s 4813.087us 1 1 100.00
chip_sw_otp_prim_tl_access 1 1 100.00
chip_prim_tl_access 144.200s 4813.087us 1 1 100.00
chip_sw_otp_ctrl_dai_lock 1 1 100.00
chip_sw_otp_ctrl_dai_lock 903.910s 9144.764us 1 1 100.00
chip_sw_pwrmgr_external_full_reset 0 1 0.00
chip_sw_pwrmgr_full_aon_reset 90.150s 3204.483us 0 1 0.00
chip_sw_pwrmgr_random_sleep_all_wake_ups 1 1 100.00
chip_sw_pwrmgr_random_sleep_all_wake_ups 1200.280s 25613.436us 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_wake_ups 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_wake_ups 393.530s 8830.742us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_por_reset 0 1 0.00
chip_sw_pwrmgr_deep_sleep_por_reset 449.380s 7647.431us 0 1 0.00
chip_sw_pwrmgr_normal_sleep_por_reset 1 1 100.00
chip_sw_pwrmgr_normal_sleep_por_reset 602.050s 7916.228us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_all_wake_ups 1 1 100.00
chip_sw_pwrmgr_deep_sleep_all_wake_ups 1245.930s 29060.735us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 0 2 0.00
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 418.660s 8983.310us 0 1 0.00
chip_sw_aon_timer_wdog_bite_reset 575.150s 8515.250us 0 1 0.00
chip_sw_pwrmgr_normal_sleep_all_reset_reqs 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_reset_reqs 1038.410s 13220.838us 1 1 100.00
chip_sw_pwrmgr_wdog_reset 1 1 100.00
chip_sw_pwrmgr_wdog_reset 582.790s 7402.016us 1 1 100.00
chip_sw_pwrmgr_power_glitch_reset 0 1 0.00
chip_sw_pwrmgr_full_aon_reset 90.150s 3204.483us 0 1 0.00
chip_sw_pwrmgr_main_power_glitch_reset 1 1 100.00
chip_sw_pwrmgr_main_power_glitch_reset 357.380s 6611.259us 1 1 100.00
chip_sw_pwrmgr_random_sleep_power_glitch_reset 0 1 0.00
chip_sw_pwrmgr_random_sleep_power_glitch_reset 283.920s 5795.158us 0 1 0.00
chip_sw_pwrmgr_deep_sleep_power_glitch_reset 1 1 100.00
chip_sw_pwrmgr_deep_sleep_power_glitch_reset 418.980s 7879.137us 1 1 100.00
chip_sw_pwrmgr_sleep_power_glitch_reset 0 1 0.00
chip_sw_pwrmgr_sleep_power_glitch_reset 233.110s 3397.034us 0 1 0.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 0 1 0.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 857.190s 14284.950us 0 1 0.00
chip_sw_pwrmgr_sysrst_ctrl_reset 2 2 100.00
chip_sw_pwrmgr_sysrst_ctrl_reset 805.310s 10272.664us 1 1 100.00
chip_sw_pwrmgr_all_reset_reqs 1325.270s 14857.804us 1 1 100.00
chip_sw_pwrmgr_b2b_sleep_reset_req 1 1 100.00
chip_sw_pwrmgr_b2b_sleep_reset_req 1943.940s 31255.729us 1 1 100.00
chip_sw_pwrmgr_sleep_disabled 1 1 100.00
chip_sw_pwrmgr_sleep_disabled 175.110s 2731.661us 1 1 100.00
chip_sw_pwrmgr_escalation_reset 1 1 100.00
chip_sw_all_escalation_resets 407.910s 6410.705us 1 1 100.00
chip_sw_rom_access 1 1 100.00
chip_sw_rom_ctrl_integrity_check 457.150s 11135.704us 1 1 100.00
chip_sw_rom_ctrl_integrity_check 1 1 100.00
chip_sw_rom_ctrl_integrity_check 457.150s 11135.704us 1 1 100.00
chip_sw_rstmgr_non_sys_reset_info 3 4 75.00
chip_sw_pwrmgr_all_reset_reqs 1325.270s 14857.804us 1 1 100.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 857.190s 14284.950us 0 1 0.00
chip_sw_pwrmgr_wdog_reset 582.790s 7402.016us 1 1 100.00
chip_sw_pwrmgr_smoketest 366.710s 6807.484us 1 1 100.00
chip_sw_rstmgr_sys_reset_info 1 1 100.00
chip_rv_dm_ndm_reset_req 466.050s 5807.346us 1 1 100.00
chip_sw_rstmgr_cpu_info 1 1 100.00
chip_sw_rstmgr_cpu_info 500.530s 6847.084us 1 1 100.00
chip_sw_rstmgr_sw_req_reset 1 1 100.00
chip_sw_rstmgr_sw_req 313.390s 5026.566us 1 1 100.00
chip_sw_rstmgr_alert_info 1 1 100.00
chip_sw_rstmgr_alert_info 1518.080s 18152.257us 1 1 100.00
chip_sw_rstmgr_sw_rst 1 1 100.00
chip_sw_rstmgr_sw_rst 190.260s 2630.556us 1 1 100.00
chip_sw_rstmgr_escalation_reset 1 1 100.00
chip_sw_all_escalation_resets 407.910s 6410.705us 1 1 100.00
chip_sw_rstmgr_alert_handler_reset_enables 1 1 100.00
chip_sw_alert_handler_lpg_reset_toggle 1356.660s 8897.312us 1 1 100.00
chip_sw_nmi_irq 1 1 100.00
chip_sw_rv_core_ibex_nmi_irq 507.390s 4954.445us 1 1 100.00
chip_sw_rv_core_ibex_rnd 1 1 100.00
chip_sw_rv_core_ibex_rnd 609.670s 5652.846us 1 1 100.00
chip_sw_rv_core_ibex_address_translation 1 1 100.00
chip_sw_rv_core_ibex_address_translation 219.600s 3441.225us 1 1 100.00
chip_sw_rv_core_ibex_icache_scrambled_access 1 1 100.00
chip_sw_rv_core_ibex_icache_invalidate 161.300s 3123.969us 1 1 100.00
chip_sw_rv_core_ibex_fault_dump 1 1 100.00
chip_sw_rstmgr_cpu_info 500.530s 6847.084us 1 1 100.00
chip_sw_rv_core_ibex_double_fault 1 1 100.00
chip_sw_rstmgr_cpu_info 500.530s 6847.084us 1 1 100.00
chip_sw_rv_core_ibex_mcounteren_writable 1 1 100.00
chip_sw_rv_core_ibex_mcounteren_writable 177.320s 3761.972us 1 1 100.00
chip_jtag_csr_rw 1 1 100.00
chip_jtag_csr_rw 845.960s 12153.900us 1 1 100.00
chip_jtag_mem_access 1 1 100.00
chip_jtag_mem_access 1262.210s 16168.819us 1 1 100.00
chip_rv_dm_ndm_reset_req 1 1 100.00
chip_rv_dm_ndm_reset_req 466.050s 5807.346us 1 1 100.00
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 0 1 0.00
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 214.410s 3354.725us 0 1 0.00
chip_rv_dm_access_after_wakeup 0 1 0.00
chip_sw_rv_dm_access_after_wakeup 1572.000s 13390.770us 0 1 0.00
chip_sw_rv_dm_jtag_tap_sel 1 1 100.00
chip_tap_straps_rma 685.190s 9892.180us 1 1 100.00
chip_rv_dm_lc_disabled 0 1 0.00
chip_rv_dm_lc_disabled 127.900s 4762.488us 0 1 0.00
chip_sw_plic_all_irqs 3 3 100.00
chip_plic_all_irqs_0 592.600s 5875.999us 1 1 100.00
chip_plic_all_irqs_10 359.380s 4938.063us 1 1 100.00
chip_plic_all_irqs_20 433.670s 4614.744us 1 1 100.00
chip_sw_plic_sw_irq 1 1 100.00
chip_sw_plic_sw_irq 196.400s 3803.009us 1 1 100.00
chip_sw_timer 1 1 100.00
chip_sw_rv_timer_irq 197.120s 3847.774us 1 1 100.00
chip_sw_spi_device_flash_mode 1 1 100.00
rom_e2e_smoke 3471.720s 17051.267us 1 1 100.00
chip_sw_spi_device_pass_through 1 1 100.00
chip_sw_spi_device_pass_through 329.830s 4179.736us 1 1 100.00
chip_sw_spi_device_pass_through_collision 0 1 0.00
chip_sw_spi_device_pass_through_collision 224.270s 4139.142us 0 1 0.00
chip_sw_spi_device_tpm 1 1 100.00
chip_sw_spi_device_tpm 250.980s 4565.590us 1 1 100.00
chip_sw_spi_host_tx_rx 1 1 100.00
chip_sw_spi_host_tx_rx 183.650s 3274.194us 1 1 100.00
chip_sw_sram_scrambled_access 2 2 100.00
chip_sw_sram_ctrl_scrambled_access 502.970s 6795.459us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 503.890s 6877.697us 1 1 100.00
chip_sw_sleep_sram_ret_contents 2 2 100.00
chip_sw_sleep_sram_ret_contents_no_scramble 599.590s 10665.039us 1 1 100.00
chip_sw_sleep_sram_ret_contents_scramble 573.810s 9731.388us 1 1 100.00
chip_sw_sram_execution 1 1 100.00
chip_sw_sram_ctrl_execution_main 663.090s 10790.298us 1 1 100.00
chip_sw_sram_lc_escalation 2 2 100.00
chip_sw_all_escalation_resets 407.910s 6410.705us 1 1 100.00
chip_sw_data_integrity_escalation 489.370s 6163.970us 1 1 100.00
chip_sw_sysrst_ctrl_reset 2 2 100.00
chip_sw_pwrmgr_sysrst_ctrl_reset 805.310s 10272.664us 1 1 100.00
chip_sw_sysrst_ctrl_reset 1250.950s 23807.106us 1 1 100.00
chip_sw_sysrst_ctrl_inputs 1 1 100.00
chip_sw_sysrst_ctrl_inputs 227.860s 2737.526us 1 1 100.00
chip_sw_sysrst_ctrl_outputs 1 1 100.00
chip_sw_sysrst_ctrl_outputs 263.330s 5072.295us 1 1 100.00
chip_sw_sysrst_ctrl_in_irq 1 1 100.00
chip_sw_sysrst_ctrl_in_irq 406.370s 4341.400us 1 1 100.00
chip_sw_sysrst_ctrl_sleep_wakeup 1 1 100.00
chip_sw_sysrst_ctrl_reset 1250.950s 23807.106us 1 1 100.00
chip_sw_sysrst_ctrl_sleep_reset 1 1 100.00
chip_sw_sysrst_ctrl_reset 1250.950s 23807.106us 1 1 100.00
chip_sw_sysrst_ctrl_ec_rst_l 1 1 100.00
chip_sw_sysrst_ctrl_ec_rst_l 2793.800s 20587.305us 1 1 100.00
chip_sw_sysrst_ctrl_flash_wp_l 1 1 100.00
chip_sw_sysrst_ctrl_ec_rst_l 2793.800s 20587.305us 1 1 100.00
chip_sw_sysrst_ctrl_ulp_z3_wakeup 1 2 50.00
chip_sw_sysrst_ctrl_ulp_z3_wakeup 438.360s 7594.603us 1 1 100.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 3081.390s 35689.132us 0 1 0.00
chip_sw_usbdev_vbus 1 1 100.00
chip_sw_usbdev_vbus 182.420s 2958.323us 1 1 100.00
chip_sw_usbdev_pullup 1 1 100.00
chip_sw_usbdev_pullup 193.560s 3207.609us 1 1 100.00
chip_sw_usbdev_aon_pullup 1 1 100.00
chip_sw_usbdev_aon_pullup 340.730s 4361.762us 1 1 100.00
chip_sw_usbdev_setup_rx 1 1 100.00
chip_sw_usbdev_setuprx 336.940s 4403.409us 1 1 100.00
chip_sw_usbdev_config_host 1 1 100.00
chip_sw_usbdev_config_host 1040.010s 8931.139us 1 1 100.00
chip_sw_usbdev_pincfg 1 1 100.00
chip_sw_usbdev_pincfg 5997.230s 31359.993us 1 1 100.00
chip_sw_usbdev_tx_rx 1 1 100.00
chip_sw_usbdev_dpi 2274.760s 12237.357us 1 1 100.00
chip_sw_usbdev_toggle_restore 1 1 100.00
chip_sw_usbdev_toggle_restore 200.370s 2859.292us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_aes_masking_off 1 1 100.00
chip_sw_aes_masking_off 246.910s 3908.499us 1 1 100.00
chip_sw_rv_core_ibex_lockstep_glitch 1 1 100.00
chip_sw_rv_core_ibex_lockstep_glitch 152.230s 2449.248us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_coremark 1 1 100.00
chip_sw_coremark 12237.320s 68427.669us 1 1 100.00
chip_sw_power_max_load 1 1 100.00
chip_sw_power_virus 1226.320s 6640.073us 1 1 100.00
rom_e2e_debug 0 3 0.00
rom_e2e_jtag_debug_test_unlocked0 258.150s 4581.695us 0 1 0.00
rom_e2e_jtag_debug_dev 241.320s 4408.737us 0 1 0.00
rom_e2e_jtag_debug_rma 261.210s 5485.911us 0 1 0.00
rom_e2e_jtag_inject 0 3 0.00
rom_e2e_jtag_inject_test_unlocked0 116.080s 3601.208us 0 1 0.00
rom_e2e_jtag_inject_dev 119.540s 3711.111us 0 1 0.00
rom_e2e_jtag_inject_rma 80.290s 2131.854us 0 1 0.00
rom_e2e_self_hash 0 1 0.00
rom_e2e_self_hash 47.325s 0.000us 0 1 0.00
chip_sw_clkmgr_jitter_cycle_measurements 0 1 0.00
chip_sw_clkmgr_jitter_frequency 390.190s 4046.038us 0 1 0.00
chip_sw_edn_boot_mode 1 1 100.00
chip_sw_edn_boot_mode 371.430s 3701.417us 1 1 100.00
chip_sw_edn_auto_mode 1 1 100.00
chip_sw_edn_auto_mode 826.550s 6083.767us 1 1 100.00
chip_sw_edn_sw_mode 1 1 100.00
chip_sw_edn_sw_mode 1418.520s 8760.711us 1 1 100.00
chip_sw_edn_kat 1 1 100.00
chip_sw_edn_kat 295.320s 2815.830us 1 1 100.00
chip_sw_flash_memory_protection 1 1 100.00
chip_sw_flash_ctrl_mem_protection 692.640s 6522.418us 1 1 100.00
chip_sw_otp_ctrl_vendor_test_csr_access 1 1 100.00
chip_sw_otp_ctrl_vendor_test_csr_access 87.140s 2670.591us 1 1 100.00
chip_sw_otp_ctrl_escalation 0 1 0.00
chip_sw_otp_ctrl_escalation 258.860s 3431.361us 0 1 0.00
chip_sw_sensor_ctrl_deep_sleep_wake_up 1 1 100.00
chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up 351.320s 6096.435us 1 1 100.00
chip_sw_pwrmgr_usb_clk_disabled_when_active 1 1 100.00
chip_sw_pwrmgr_usb_clk_disabled_when_active 466.480s 7069.820us 1 1 100.00
chip_sw_all_resets 1 1 100.00
chip_sw_pwrmgr_all_reset_reqs 1325.270s 14857.804us 1 1 100.00
chip_rv_dm_perform_debug 0 3 0.00
rom_e2e_jtag_debug_test_unlocked0 258.150s 4581.695us 0 1 0.00
rom_e2e_jtag_debug_dev 241.320s 4408.737us 0 1 0.00
rom_e2e_jtag_debug_rma 261.210s 5485.911us 0 1 0.00
chip_sw_rv_dm_access_after_hw_reset 1 1 100.00
chip_sw_rv_dm_access_after_escalation_reset 392.720s 5189.263us 1 1 100.00
chip_sw_plic_alerts 1 1 100.00
chip_sw_all_escalation_resets 407.910s 6410.705us 1 1 100.00
tick_configuration 1 1 100.00
chip_sw_rv_timer_systick_test 6130.250s 39049.084us 1 1 100.00
counter_wrap 1 1 100.00
chip_sw_rv_timer_systick_test 6130.250s 39049.084us 1 1 100.00
chip_sw_spi_device_output_when_disabled_or_sleeping 1 1 100.00
chip_sw_spi_device_pinmux_sleep_retention 293.040s 4560.131us 1 1 100.00
chip_sw_uart_watermarks 1 1 100.00
chip_sw_uart_tx_rx 388.640s 5257.082us 1 1 100.00
chip_sw_usbdev_stream 1 1 100.00
chip_sw_usbdev_stream 3584.670s 18683.878us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 7 11 63.64
chip_sival_flash_info_access 230.990s 3880.267us 1 1 100.00
chip_sw_rstmgr_rst_cnsty_escalation 19.130s 10.300us 0 1 0.00
chip_sw_otp_ctrl_rot_auth_config 7.720s 0.000us 0 1 0.00
chip_sw_otp_ctrl_ecc_error_vendor_test 186.140s 3580.645us 1 1 100.00
chip_sw_otp_ctrl_descrambling 272.150s 4068.022us 1 1 100.00
chip_sw_pwrmgr_lowpower_cancel 281.400s 4395.077us 1 1 100.00
chip_sw_pwrmgr_sleep_wake_5_bug 8.181s 0.000us 0 1 0.00
chip_sw_flash_ctrl_write_clear 268.630s 3882.835us 1 1 100.00
ate_bootstrap_flash_erase 651.430s 10010.300us 0 1 0.00
ate_bootstrap_one_frame 7302.600s 43263.413us 1 1 100.00
ate_bootstrap_disjoint 10186.390s 78778.778us 1 1 100.00

Error Messages

   Test seed line log context
Error-[NOA] Null object access 7 test runs
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 5511628198210973642414439135057841708925281240888867861615730067363572494888 330
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_debug_test_unlocked0 14171462296403821765199442478969623543672032892129925911479116953610453201243 322
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_debug_dev 64123258793876322322674668187757796864696793857882756656306966365724920989062 322
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_debug_rma 87949794192247715914944070223571571163832571947324327809758198939395030833327 322
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_test_unlocked0 7663394889721933091933737353320732092824404482118535708481934071024309682027 308
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_dev 34066196261294337637937810611532173896847213538853122963900564891130673069696 308
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_rma 57799607050922082180611011759683804235256879285000750104812719398635964296770 306
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
Offending '(rstreqs[*] && (reset_cause == HwReq))' 5 test runs
chip_sw_pwrmgr_random_sleep_all_reset_reqs 99013271600669626625254755503271269906679892064482375926560912358131927962916 347
UVM_ERROR @ 14284.950000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 14284.950000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 89535413253947184521273609184399731589213145939062163619187508774371234503340 330
UVM_ERROR @ 8983.310500 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 8983.310500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_deep_sleep_por_reset 77480501368711807769737365769539812667869003394966959157489643698112870771303 328
UVM_ERROR @ 7647.431000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 7647.431000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_random_sleep_power_glitch_reset 112856510685031485894627798767835764384227279599801342799481088878954729332778 319
UVM_ERROR @ 5795.158000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 5795.158000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_aon_timer_wdog_bite_reset 15229184778840641055520807306679773913032927108144182558940139427355890582861 322
UVM_ERROR @ 8515.250000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 8515.250000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [lc_walkthrough_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected 3 test runs
chip_sw_lc_walkthrough_dev 86465494377453601595443149683450162230607078770719840706414295031950717896785 372
UVM_INFO @ 10652.331544 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_walkthrough_prod 102033240887790600784160707300630553576731719469174286925725108258486328476913 372
UVM_INFO @ 13057.371556 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_walkthrough_rma 93345879594475540432086226882999966694828403954169197335914881096173765845953 344
UVM_INFO @ 8870.628228 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:322) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns 2 test runs
chip_sw_hmac_multistream 80852419095881204429594859633925652164428864244229982550154640637107861019928 357
UVM_INFO @ 12018.672195 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_keymgr_sideload_otbn 17975727964328681598380040594843125158289788409461407817973322681419041277224 337
UVM_INFO @ 20026.909122 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:615) scoreboard [scoreboard] On interface chip_reg_block, item had unexpected d_error value(predicted *, but saw *). 2 test runs
chip_tl_errors 15651358542173436674508986410611090542464499184873339075492474823611989448932 220
TL item was: req: (cip_tl_seq_item@31899) { a_addr: 'h105e0 a_data: 'he35426cc a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h1 a_opcode: 'h4 a_user: 'h19218 d_param: 'h0 d_source: 'h1 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2357.428860 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_csr_mem_rw_with_rand_reset 110265551043185871325369072025199378511709148053171077348865226514847823766912 227
TL item was: req: (cip_tl_seq_item@31851) { a_addr: 'h104d0 a_data: 'hebae5386 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h7 a_opcode: 'h4 a_user: 'h1a913 d_param: 'h0 d_source: 'h7 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2855.754376 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$'] 2 test runs
chip_sw_pwrmgr_sleep_wake_5_bug 61800888192180762768557330991527385294977763463578987697895484051359318448564 None
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_self_hash 105513089496592789313156973835199494103221612267644725452747812096017462912105 None
Another command (pid=422958) is running. Waiting for it to complete on the server (server_pid=267567)...
Another command (pid=389376) is running. Waiting for it to complete on the server (server_pid=267567)...
Another command (pid=467977) is running. Waiting for it to complete on the server (server_pid=267567)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
UVM_FATAL @ * us: (sec_cm_pkg.sv:48) [sec_cm_pkg::find_sec_cm_if_proxy] no proxy with path *rstmgr.u_d0_spi_host*.leaf_rst_path 1 test run
chip_sw_rstmgr_rst_cnsty_escalation 102588560035385855568255104582928144441765171898082704387742111890840509400850 304
UVM_INFO @ 10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty 1 test run
chip_sw_spi_device_pass_through_collision 39199458697924306836182161028475603762824326937750271385390109073301427800013 330
UVM_INFO @ 4139.142179 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [flash_ctrl_lc_rw_en_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected 1 test run
chip_sw_flash_ctrl_lc_rw_en 49542169252156082187410966983263810180484606950789844191531538265926174683108 312
UVM_INFO @ 4060.837396 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to * 1 test run
chip_sw_otp_ctrl_lc_signals_rma 49791350753784852908432593886014481558507507197545292265057782143792949573444 345
UVM_INFO @ 9857.092632 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))' 1 test run
chip_sw_otp_ctrl_escalation 40992854478661986714340495629976064118017846901232519546705245244778462613354 319
UVM_ERROR @ 3431.361406 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 3431.361406 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[Otp]] file otp_img_test_unlocked0_manuf_empty.*.vmem could not be opened for r mode 1 test run
chip_sw_otp_ctrl_rot_auth_config 54385762281500854854841307083766802625930160682088161776821928116444457549302 285
UVM_INFO @ 0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_base_vseq.sv:864) virtual_sequencer [chip_sw_lc_volatile_raw_unlock_vseq] max attempt reached to get lc status LcExtClockSwitched! 1 test run
chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz 50890727987273382386696252095101000768782921552917049848868647823188301404131 312
UVM_INFO @ 26471.111749 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '((~rst_ni) === (~seed_en_q))' 1 test run
chip_sw_pwrmgr_full_aon_reset 78442296090094184716526620540301937743761577391174365362498597411006939646440 306
UVM_ERROR @ 3204.483490 us: (otbn_rnd.sv:233) [ASSERT FAILED] UrndNoReseedOnReset_A
UVM_INFO @ 3204.483490 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(!$fell((pwrmgr_data_o.done == MuBi4True)))' 1 test run
chip_sw_pwrmgr_sleep_power_glitch_reset 36850826631672325561141605372628759354135320543739193071105028498474048171960 316
UVM_ERROR @ 3397.033960 us: (rom_ctrl.sv:590) [ASSERT FAILED] PwrmgrDataChk_A
UVM_INFO @ 3397.033960 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:322) virtual_sequencer [chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns 1 test run
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 52447181513212377694527786322185460631519730118600992454777723070396952682061 335
UVM_INFO @ 35689.132113 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:351)] CHECK-fail: Expect alert *! 1 test run
chip_sw_alert_test 72516957525201299636942146737506837419448811292771982102467225662834195601356 310
UVM_INFO @ 3468.145146 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0) 1 test run
chip_sw_alert_handler_lpg_sleep_mode_alerts 30725701659113237731365861041495509004668780031653669756374962601317062505015 311
UVM_INFO @ 3164.110624 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes 1 test run
chip_sw_alert_handler_lpg_sleep_mode_pings 36638130086968673044957694623048079702788149506556157879993949406697120695969 None
UVM_ERROR @ * us: (sw_logger_if.sv:526) [clkmgr_jitter_frequency_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected 1 test run
chip_sw_clkmgr_jitter_frequency 39000009520358593374964128273230674831374302227766882524863464980568977708323 346
UVM_INFO @ 4046.037649 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_rv_dm_access_after_wakeup_vseq.sv:93) [chip_sw_rv_dm_access_after_wakeup_vseq] Timed out waiting for device to wakeup from deep sleep. 1 test run
chip_sw_rv_dm_access_after_wakeup 98434975715996211473341100420823874115228562453866803934065493800118227929855 332
UVM_INFO @ 13390.770088 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_vseq.sv:660) [chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch 1 test run
chip_rv_dm_lc_disabled 22294895148917551958428838912218190286980273089109643867810228543329685887978 228
UVM_INFO @ 4762.487875 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_power_idle_load_vseq.sv:24) [chip_sw_power_idle_load_vseq] timeout waiting for SW sync GPIO (*) 1 test run
chip_sw_power_idle_load 113726129318081138534986811921659935859841281719487412263849129667752564111907 321
UVM_INFO @ 15303.342160 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_power_sleep_load_vseq.sv:47) [chip_sw_power_sleep_load_vseq] timeout waiting for SW sync GPIO (*) 1 test run
chip_sw_power_sleep_load 67918938105598174459763629765702838285391197686955284361246017677920766390029 332
UVM_INFO @ 15673.142515 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/lib/testing/autogen/isr_testutils.c:41)] CHECK-fail: Only adc_ctrl IRQ * expected to fire. Actual IRQ state = * 1 test run
chip_sw_ast_clk_rst_inputs 103886374371040261997851307613079625437896738028790209221813439247795502140607 330
UVM_INFO @ 15698.275025 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (csr_utils_pkg.sv:619) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout chip_reg_block.spi_device.cmd_info_*.opcode (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=1) 1 test run
ate_bootstrap_flash_erase 32625713072625725405671008205464686850456081235684423258735006277553076181689 275
UVM_INFO @ 10010.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rom_e2e_keymgr_init_otp_invalid_meas_sim_dv(sw/device/silicon_creator/rom/e2e/keymgr/rom_e2e_keymgr_init_test.c:38)] DIF-fail: dif_otp_ctrl_get_digest( &otp_ctrl, kDifOtpCtrlPartitionCreatorSwCfg, &creator_digest) returns * 1 test run
rom_e2e_keymgr_init_rom_ext_invalid_meas 48876137767137570705299212660035637966499248720423580859198320590092258209365 322
UVM_INFO @ 23902.688860 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '$stable(key_data_i)' 1 test run
rom_keymgr_functest 77215055540538132953638804578508296224921935920510519975615198053171386167234 330
UVM_ERROR @ 6800.716036 us: (kmac_core.sv:464) [ASSERT FAILED] KeyDataStableWhenValid_M
UVM_INFO @ 6800.716036 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---