Simulation Results: clkmgr

 
10/08/2026 15:30:36 DVSim: v1.50.1 sha: af43bb2 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 92.54 %
  • code
  • 97.78 %
  • assert
  • 94.07 %
  • func
  • 85.76 %
  • line
  • 98.88 %
  • branch
  • 98.53 %
  • cond
  • 92.28 %
  • toggle
  • 99.19 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
83.33%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
clkmgr_smoke 0.830s 57.557us 1 1 100.00
csr_hw_reset 1 1 100.00
clkmgr_csr_hw_reset 0.850s 29.160us 1 1 100.00
csr_rw 1 1 100.00
clkmgr_csr_rw 0.840s 15.523us 1 1 100.00
csr_bit_bash 1 1 100.00
clkmgr_csr_bit_bash 9.350s 2448.204us 1 1 100.00
csr_aliasing 1 1 100.00
clkmgr_csr_aliasing 1.920s 322.128us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
clkmgr_csr_mem_rw_with_rand_reset 1.140s 30.295us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
clkmgr_csr_rw 0.840s 15.523us 1 1 100.00
clkmgr_csr_aliasing 1.920s 322.128us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 1 1 100.00
clkmgr_peri 0.810s 15.178us 1 1 100.00
trans_enables 1 1 100.00
clkmgr_trans 1.060s 50.926us 1 1 100.00
extclk 1 1 100.00
clkmgr_extclk 0.800s 37.379us 1 1 100.00
clk_status 1 1 100.00
clkmgr_clk_status 0.710s 17.072us 1 1 100.00
jitter 1 1 100.00
clkmgr_smoke 0.830s 57.557us 1 1 100.00
frequency 1 1 100.00
clkmgr_frequency 8.970s 2361.333us 1 1 100.00
frequency_timeout 1 1 100.00
clkmgr_frequency_timeout 3.560s 986.106us 1 1 100.00
frequency_overflow 1 1 100.00
clkmgr_frequency 8.970s 2361.333us 1 1 100.00
stress_all 1 1 100.00
clkmgr_stress_all 18.440s 7797.146us 1 1 100.00
alert_test 1 1 100.00
clkmgr_alert_test 0.700s 13.414us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
clkmgr_tl_errors 1.400s 91.101us 1 1 100.00
tl_d_illegal_access 1 1 100.00
clkmgr_tl_errors 1.400s 91.101us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
clkmgr_csr_hw_reset 0.850s 29.160us 1 1 100.00
clkmgr_csr_rw 0.840s 15.523us 1 1 100.00
clkmgr_csr_aliasing 1.920s 322.128us 1 1 100.00
clkmgr_same_csr_outstanding 1.260s 115.956us 1 1 100.00
tl_d_partial_access 4 4 100.00
clkmgr_csr_hw_reset 0.850s 29.160us 1 1 100.00
clkmgr_csr_rw 0.840s 15.523us 1 1 100.00
clkmgr_csr_aliasing 1.920s 322.128us 1 1 100.00
clkmgr_same_csr_outstanding 1.260s 115.956us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 1 2 50.00
clkmgr_sec_cm 22.560s 10081.952us 0 1 0.00
clkmgr_tl_intg_err 2.930s 630.412us 1 1 100.00
shadow_reg_update_error 1 1 100.00
clkmgr_shadow_reg_errors 1.170s 76.163us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
clkmgr_shadow_reg_errors 1.170s 76.163us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
clkmgr_shadow_reg_errors 1.170s 76.163us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
clkmgr_shadow_reg_errors 1.170s 76.163us 1 1 100.00
shadow_reg_update_error_with_csr_rw 0 1 0.00
clkmgr_shadow_reg_errors_with_csr_rw 343.730s 200000.000us 0 1 0.00
sec_cm_bus_integrity 1 1 100.00
clkmgr_tl_intg_err 2.930s 630.412us 1 1 100.00
sec_cm_meas_clk_bkgn_chk 1 1 100.00
clkmgr_frequency 8.970s 2361.333us 1 1 100.00
sec_cm_timeout_clk_bkgn_chk 1 1 100.00
clkmgr_frequency_timeout 3.560s 986.106us 1 1 100.00
sec_cm_meas_config_shadow 1 1 100.00
clkmgr_shadow_reg_errors 1.170s 76.163us 1 1 100.00
sec_cm_idle_intersig_mubi 1 1 100.00
clkmgr_idle_intersig_mubi 0.870s 45.121us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
clkmgr_lc_ctrl_intersig_mubi 0.790s 52.066us 1 1 100.00
sec_cm_lc_ctrl_clk_handshake_intersig_mubi 1 1 100.00
clkmgr_lc_clk_byp_req_intersig_mubi 0.730s 20.589us 1 1 100.00
sec_cm_clk_handshake_intersig_mubi 1 1 100.00
clkmgr_clk_handshake_intersig_mubi 0.810s 31.411us 1 1 100.00
sec_cm_div_intersig_mubi 1 1 100.00
clkmgr_div_intersig_mubi 0.690s 17.937us 1 1 100.00
sec_cm_jitter_config_mubi 1 1 100.00
clkmgr_csr_rw 0.840s 15.523us 1 1 100.00
sec_cm_idle_ctr_redun 0 1 0.00
clkmgr_sec_cm 22.560s 10081.952us 0 1 0.00
sec_cm_meas_config_regwen 1 1 100.00
clkmgr_csr_rw 0.840s 15.523us 1 1 100.00
sec_cm_clk_ctrl_config_regwen 1 1 100.00
clkmgr_csr_rw 0.840s 15.523us 1 1 100.00
prim_count_check 0 1 0.00
clkmgr_sec_cm 22.560s 10081.952us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 1 1 100.00
clkmgr_regwen 3.580s 769.565us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
clkmgr_stress_all_with_rand_reset 54.780s 9019.423us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 1 test run
clkmgr_shadow_reg_errors_with_csr_rw 54488216205965303898986321438555242541496349641772909052419077991605577818894 76
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1077) virtual_sequencer [clkmgr_common_vseq] Timeout waiting for end of ack for alert fatal_fault 1 test run
clkmgr_sec_cm 88853490262115250032835377610488103225734835420783386408222822630106080357065 92
UVM_INFO @ 10081951707 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---