Simulation Results: edn/edn0

 
10/08/2026 15:30:36 DVSim: v1.50.1 sha: af43bb2 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 87.18 %
  • code
  • 83.40 %
  • assert
  • 97.40 %
  • func
  • 80.75 %
  • line
  • 97.61 %
  • branch
  • 92.19 %
  • cond
  • 87.46 %
  • toggle
  • 86.52 %
  • FSM
  • 53.23 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.880s 25.613us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.880s 96.275us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.800s 25.556us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 2.730s 85.068us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.150s 75.353us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 0.950s 20.273us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.800s 25.556us 1 1 100.00
edn_csr_aliasing 1.150s 75.353us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.280s 34.744us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.280s 34.744us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.280s 34.744us 1 1 100.00
interrupts 1 1 100.00
edn_intr 0.780s 34.498us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.360s 25.562us 1 1 100.00
errs 1 1 100.00
edn_err 0.790s 29.653us 1 1 100.00
disable 2 2 100.00
edn_disable 0.860s 41.329us 1 1 100.00
edn_disable_auto_req_mode 1.030s 35.951us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 3.030s 1320.109us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.800s 26.749us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 0.820s 44.330us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 1.460s 69.517us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 1.460s 69.517us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.880s 96.275us 1 1 100.00
edn_csr_rw 0.800s 25.556us 1 1 100.00
edn_csr_aliasing 1.150s 75.353us 1 1 100.00
edn_same_csr_outstanding 0.870s 15.661us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.880s 96.275us 1 1 100.00
edn_csr_rw 0.800s 25.556us 1 1 100.00
edn_csr_aliasing 1.150s 75.353us 1 1 100.00
edn_same_csr_outstanding 0.870s 15.661us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 4.080s 1163.489us 1 1 100.00
edn_tl_intg_err 1.990s 187.816us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.810s 109.894us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.360s 25.562us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 4.080s 1163.489us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 4.080s 1163.489us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 4.080s 1163.489us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 4.080s 1163.489us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.360s 25.562us 1 1 100.00
edn_sec_cm 4.080s 1163.489us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.360s 25.562us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.990s 187.816us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 53.970s 13901.065us 1 1 100.00