Simulation Results: edn/edn1

 
10/08/2026 15:30:36 DVSim: v1.50.1 sha: af43bb2 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 85.42 %
  • code
  • 79.50 %
  • assert
  • 97.14 %
  • func
  • 79.62 %
  • line
  • 96.97 %
  • branch
  • 90.26 %
  • cond
  • 86.62 %
  • toggle
  • 87.29 %
  • FSM
  • 36.36 %
Validation stages
V1
100.00%
V2
92.86%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.800s 17.197us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.810s 52.083us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.770s 57.297us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 1.860s 544.817us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.040s 24.780us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.190s 41.066us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.770s 57.297us 1 1 100.00
edn_csr_aliasing 1.040s 24.780us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 0.940s 54.603us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 0.940s 54.603us 1 1 100.00
genbits 1 1 100.00
edn_genbits 0.940s 54.603us 1 1 100.00
interrupts 1 1 100.00
edn_intr 0.770s 63.711us 1 1 100.00
alerts 1 1 100.00
edn_alert 0.980s 54.102us 1 1 100.00
errs 1 1 100.00
edn_err 1.000s 44.303us 1 1 100.00
disable 1 2 50.00
edn_disable 0.710s 29.466us 1 1 100.00
edn_disable_auto_req_mode 4.700s 500.000us 0 1 0.00
stress_all 1 1 100.00
edn_stress_all 3.100s 3319.689us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.780s 19.535us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 0.870s 74.585us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 1.710s 315.843us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 1.710s 315.843us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.810s 52.083us 1 1 100.00
edn_csr_rw 0.770s 57.297us 1 1 100.00
edn_csr_aliasing 1.040s 24.780us 1 1 100.00
edn_same_csr_outstanding 0.950s 36.801us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.810s 52.083us 1 1 100.00
edn_csr_rw 0.770s 57.297us 1 1 100.00
edn_csr_aliasing 1.040s 24.780us 1 1 100.00
edn_same_csr_outstanding 0.950s 36.801us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 3.950s 656.680us 1 1 100.00
edn_tl_intg_err 1.240s 191.441us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.800s 33.431us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 0.980s 54.102us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 3.950s 656.680us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 3.950s 656.680us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 3.950s 656.680us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 3.950s 656.680us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 0.980s 54.102us 1 1 100.00
edn_sec_cm 3.950s 656.680us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 0.980s 54.102us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.240s 191.441us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 68.320s 6829.358us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 1 test run
edn_disable_auto_req_mode 114353427863759943694027788856412879212304888314813146240834650091328705406770 88
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---