Simulation Results: entropy_src/rng_4bits

 
10/08/2026 15:30:36 DVSim: v1.50.1 sha: af43bb2 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 75.33 %
  • code
  • 89.03 %
  • assert
  • 84.73 %
  • func
  • 52.23 %
  • block
  • 94.47 %
  • line
  • 97.21 %
  • branch
  • 86.75 %
  • toggle
  • 76.33 %
  • FSM
  • 95.83 %
Validation stages
V1
83.33%
V2
100.00%
V2S
100.00%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
entropy_src_smoke 2.000s 26.481us 1 1 100.00
csr_hw_reset 1 1 100.00
entropy_src_csr_hw_reset 1.000s 42.970us 1 1 100.00
csr_rw 1 1 100.00
entropy_src_csr_rw 2.000s 33.026us 1 1 100.00
csr_bit_bash 1 1 100.00
entropy_src_csr_bit_bash 11.000s 825.039us 1 1 100.00
csr_aliasing 1 1 100.00
entropy_src_csr_aliasing 2.000s 76.564us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
entropy_src_csr_mem_rw_with_rand_reset 1.000s 5.287us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
entropy_src_csr_rw 2.000s 33.026us 1 1 100.00
entropy_src_csr_aliasing 2.000s 76.564us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 3 3 100.00
entropy_src_smoke 2.000s 26.481us 1 1 100.00
entropy_src_rng 55.000s 13236.544us 1 1 100.00
entropy_src_fw_ov 226.000s 14038.305us 1 1 100.00
firmware_mode 1 1 100.00
entropy_src_fw_ov 226.000s 14038.305us 1 1 100.00
rng_mode 1 1 100.00
entropy_src_rng 55.000s 13236.544us 1 1 100.00
rng_max_rate 1 1 100.00
entropy_src_rng_max_rate 335.000s 13044.658us 1 1 100.00
health_checks 1 1 100.00
entropy_src_rng 55.000s 13236.544us 1 1 100.00
conditioning 1 1 100.00
entropy_src_rng 55.000s 13236.544us 1 1 100.00
interrupts 2 2 100.00
entropy_src_rng 55.000s 13236.544us 1 1 100.00
entropy_src_intr 11.000s 507.928us 1 1 100.00
alerts 2 2 100.00
entropy_src_rng 55.000s 13236.544us 1 1 100.00
entropy_src_functional_alerts 4.000s 744.976us 1 1 100.00
stress_all 1 1 100.00
entropy_src_stress_all 49.000s 14417.045us 1 1 100.00
functional_errors 1 1 100.00
entropy_src_functional_errors 2.000s 80.893us 1 1 100.00
firmware_ov_read_contiguous_data 1 1 100.00
entropy_src_fw_ov_contiguous 3.000s 173.354us 1 1 100.00
intr_test 1 1 100.00
entropy_src_intr_test 1.000s 58.779us 1 1 100.00
alert_test 1 1 100.00
entropy_src_alert_test 1.000s 43.201us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
entropy_src_tl_errors 2.000s 233.982us 1 1 100.00
tl_d_illegal_access 1 1 100.00
entropy_src_tl_errors 2.000s 233.982us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
entropy_src_csr_hw_reset 1.000s 42.970us 1 1 100.00
entropy_src_csr_rw 2.000s 33.026us 1 1 100.00
entropy_src_csr_aliasing 2.000s 76.564us 1 1 100.00
entropy_src_same_csr_outstanding 2.000s 36.655us 1 1 100.00
tl_d_partial_access 4 4 100.00
entropy_src_csr_hw_reset 1.000s 42.970us 1 1 100.00
entropy_src_csr_rw 2.000s 33.026us 1 1 100.00
entropy_src_csr_aliasing 2.000s 76.564us 1 1 100.00
entropy_src_same_csr_outstanding 2.000s 36.655us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
entropy_src_sec_cm 3.000s 101.824us 1 1 100.00
entropy_src_tl_intg_err 3.000s 115.812us 1 1 100.00
sec_cm_config_regwen 2 2 100.00
entropy_src_rng 55.000s 13236.544us 1 1 100.00
entropy_src_cfg_regwen 1.000s 63.373us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
entropy_src_rng 55.000s 13236.544us 1 1 100.00
sec_cm_config_redun 1 1 100.00
entropy_src_rng 55.000s 13236.544us 1 1 100.00
sec_cm_intersig_mubi 2 2 100.00
entropy_src_rng 55.000s 13236.544us 1 1 100.00
entropy_src_fw_ov 226.000s 14038.305us 1 1 100.00
sec_cm_main_sm_fsm_sparse 2 2 100.00
entropy_src_functional_errors 2.000s 80.893us 1 1 100.00
entropy_src_sec_cm 3.000s 101.824us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 2 2 100.00
entropy_src_functional_errors 2.000s 80.893us 1 1 100.00
entropy_src_sec_cm 3.000s 101.824us 1 1 100.00
sec_cm_rng_bkgn_chk 1 1 100.00
entropy_src_rng 55.000s 13236.544us 1 1 100.00
sec_cm_fifo_ctr_redun 2 2 100.00
entropy_src_functional_errors 2.000s 80.893us 1 1 100.00
entropy_src_sec_cm 3.000s 101.824us 1 1 100.00
sec_cm_ctr_redun 2 2 100.00
entropy_src_functional_errors 2.000s 80.893us 1 1 100.00
entropy_src_sec_cm 3.000s 101.824us 1 1 100.00
sec_cm_ctr_local_esc 1 1 100.00
entropy_src_functional_errors 2.000s 80.893us 1 1 100.00
sec_cm_esfinal_rdata_bus_consistency 1 1 100.00
entropy_src_functional_alerts 4.000s 744.976us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
entropy_src_tl_intg_err 3.000s 115.812us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
external_health_tests 1 1 100.00
entropy_src_rng_with_xht_rsps 58.000s 13288.203us 1 1 100.00
stress_all_with_rand_reset 0 1 0.00
entropy_src_stress_all_with_rand_reset 14.000s 6478.433us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (entropy_src_scoreboard.sv:1663) scoreboard [scoreboard] invalid csr: entropy_src_reg_block.extht_lo_threshold 1 test run
entropy_src_stress_all_with_rand_reset 53921469407089132862435006556022535574593244345857433899132210231638052541792 123
UVM_INFO @ 6478433209 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (entropy_src_base_vseq.sv:83) virtual_sequencer [mirror] Failed to mirror alert_fail_counts 1 test run
entropy_src_csr_mem_rw_with_rand_reset 62747442479992141022904587671874483465453621568763727189408165665908251005861 113
UVM_INFO @ 5287212 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---