Simulation Results: flash_ctrl

 
10/08/2026 15:30:36 DVSim: v1.50.1 sha: af43bb2 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.62 %
  • code
  • 93.94 %
  • assert
  • 97.02 %
  • func
  • 95.91 %
  • line
  • 95.95 %
  • branch
  • 97.16 %
  • cond
  • 94.02 %
  • toggle
  • 96.17 %
  • FSM
  • 86.39 %
Validation stages
V1
100.00%
V2
98.28%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
flash_ctrl_smoke 80.940s 28.228us 1 1 100.00
smoke_hw 1 1 100.00
flash_ctrl_smoke_hw 13.500s 52.990us 1 1 100.00
csr_hw_reset 1 1 100.00
flash_ctrl_csr_hw_reset 16.070s 210.607us 1 1 100.00
csr_rw 1 1 100.00
flash_ctrl_csr_rw 9.560s 34.337us 1 1 100.00
csr_bit_bash 1 1 100.00
flash_ctrl_csr_bit_bash 37.220s 2548.266us 1 1 100.00
csr_aliasing 1 1 100.00
flash_ctrl_csr_aliasing 26.570s 3194.556us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
flash_ctrl_csr_mem_rw_with_rand_reset 10.460s 81.697us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
flash_ctrl_csr_rw 9.560s 34.337us 1 1 100.00
flash_ctrl_csr_aliasing 26.570s 3194.556us 1 1 100.00
mem_walk 1 1 100.00
flash_ctrl_mem_walk 6.380s 121.635us 1 1 100.00
mem_partial_access 1 1 100.00
flash_ctrl_mem_partial_access 10.440s 59.092us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sw_op 1 1 100.00
flash_ctrl_sw_op 11.970s 23.291us 1 1 100.00
host_read_direct 1 1 100.00
flash_ctrl_host_dir_rd 29.320s 41.728us 1 1 100.00
rma_hw_if 3 3 100.00
flash_ctrl_hw_rma 1201.510s 355945.228us 1 1 100.00
flash_ctrl_hw_rma_reset 542.430s 230230.623us 1 1 100.00
flash_ctrl_lcmgr_intg 6.500s 42.886us 1 1 100.00
host_controller_arb 1 1 100.00
flash_ctrl_host_ctrl_arb 1228.510s 264051.755us 1 1 100.00
erase_suspend 1 1 100.00
flash_ctrl_erase_suspend 199.440s 4117.219us 1 1 100.00
program_reset 1 1 100.00
flash_ctrl_prog_reset 6.010s 47.338us 1 1 100.00
full_memory_access 1 1 100.00
flash_ctrl_full_mem_access 1878.130s 511717.426us 1 1 100.00
rd_buff_eviction 1 1 100.00
flash_ctrl_rd_buff_evict 42.660s 61.459us 1 1 100.00
rd_buff_eviction_w_ecc 3 3 100.00
flash_ctrl_rw_evict 16.390s 50.288us 1 1 100.00
flash_ctrl_rw_evict_all_en 17.540s 30.081us 1 1 100.00
flash_ctrl_re_evict 17.760s 272.953us 1 1 100.00
host_arb 1 1 100.00
flash_ctrl_phy_arb 81.980s 2779.323us 1 1 100.00
host_interleave 1 1 100.00
flash_ctrl_phy_arb 81.980s 2779.323us 1 1 100.00
memory_protection 1 1 100.00
flash_ctrl_mp_regions 265.860s 19343.363us 1 1 100.00
fetch_code 1 1 100.00
flash_ctrl_fetch_code 10.850s 284.767us 1 1 100.00
all_partitions 1 1 100.00
flash_ctrl_rand_ops 604.010s 1659.982us 1 1 100.00
error_mp 1 1 100.00
flash_ctrl_error_mp 427.870s 40978.820us 1 1 100.00
error_prog_win 1 1 100.00
flash_ctrl_error_prog_win 350.770s 431.417us 1 1 100.00
error_prog_type 1 1 100.00
flash_ctrl_error_prog_type 974.770s 2251.449us 1 1 100.00
error_read_seed 1 1 100.00
flash_ctrl_hw_read_seed_err 5.910s 40.309us 1 1 100.00
read_write_overflow 1 1 100.00
flash_ctrl_oversize_error 124.370s 13465.658us 1 1 100.00
flash_ctrl_disable 1 1 100.00
flash_ctrl_disable 14.670s 34.460us 1 1 100.00
flash_ctrl_connect 1 1 100.00
flash_ctrl_connect 8.740s 25.136us 1 1 100.00
stress_all 1 1 100.00
flash_ctrl_stress_all 861.510s 505.944us 1 1 100.00
secret_partition 2 2 100.00
flash_ctrl_hw_sec_otp 80.470s 10811.743us 1 1 100.00
flash_ctrl_otp_reset 59.790s 41.844us 1 1 100.00
isolation_partition 1 1 100.00
flash_ctrl_hw_rma 1201.510s 355945.228us 1 1 100.00
interrupts 4 4 100.00
flash_ctrl_intr_rd 116.680s 1615.736us 1 1 100.00
flash_ctrl_intr_wr 49.270s 6271.451us 1 1 100.00
flash_ctrl_intr_rd_slow_flash 119.400s 33072.038us 1 1 100.00
flash_ctrl_intr_wr_slow_flash 178.900s 584281.261us 1 1 100.00
invalid_op 1 1 100.00
flash_ctrl_invalid_op 47.100s 5821.318us 1 1 100.00
mid_op_rst 1 1 100.00
flash_ctrl_mid_op_rst 39.230s 1244.361us 1 1 100.00
double_bit_err 5 5 100.00
flash_ctrl_read_word_sweep_derr 16.020s 31.698us 1 1 100.00
flash_ctrl_ro_derr 88.370s 758.561us 1 1 100.00
flash_ctrl_rw_derr 151.730s 4826.041us 1 1 100.00
flash_ctrl_derr_detect 102.030s 718.745us 1 1 100.00
flash_ctrl_integrity 319.090s 4707.640us 1 1 100.00
single_bit_err 3 3 100.00
flash_ctrl_read_word_sweep_serr 12.640s 29.551us 1 1 100.00
flash_ctrl_ro_serr 99.890s 3426.464us 1 1 100.00
flash_ctrl_rw_serr 163.650s 18754.179us 1 1 100.00
singlebit_err_counter 0 1 0.00
flash_ctrl_serr_counter 3603.788s 0.000us 0 1 0.00
singlebit_err_address 1 1 100.00
flash_ctrl_serr_address 52.370s 7898.264us 1 1 100.00
scramble 5 5 100.00
flash_ctrl_wo 99.440s 2460.376us 1 1 100.00
flash_ctrl_write_word_sweep 7.260s 155.450us 1 1 100.00
flash_ctrl_read_word_sweep 8.110s 55.629us 1 1 100.00
flash_ctrl_ro 98.020s 1934.508us 1 1 100.00
flash_ctrl_rw 384.550s 18230.189us 1 1 100.00
filesystem_support 1 1 100.00
flash_ctrl_fs_sup 20.850s 566.125us 1 1 100.00
rma_write_process_error 2 2 100.00
flash_ctrl_rma_err 539.230s 42417.503us 1 1 100.00
flash_ctrl_hw_prog_rma_wipe_err 20.410s 10103.021us 1 1 100.00
alert_test 1 1 100.00
flash_ctrl_alert_test 6.310s 81.427us 1 1 100.00
intr_test 1 1 100.00
flash_ctrl_intr_test 6.510s 89.857us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
flash_ctrl_tl_errors 15.360s 70.349us 1 1 100.00
tl_d_illegal_access 1 1 100.00
flash_ctrl_tl_errors 15.360s 70.349us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
flash_ctrl_csr_hw_reset 16.070s 210.607us 1 1 100.00
flash_ctrl_csr_rw 9.560s 34.337us 1 1 100.00
flash_ctrl_csr_aliasing 26.570s 3194.556us 1 1 100.00
flash_ctrl_same_csr_outstanding 18.940s 586.852us 1 1 100.00
tl_d_partial_access 4 4 100.00
flash_ctrl_csr_hw_reset 16.070s 210.607us 1 1 100.00
flash_ctrl_csr_rw 9.560s 34.337us 1 1 100.00
flash_ctrl_csr_aliasing 26.570s 3194.556us 1 1 100.00
flash_ctrl_same_csr_outstanding 18.940s 586.852us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
flash_ctrl_shadow_reg_errors 16.810s 16.821us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
flash_ctrl_shadow_reg_errors 16.810s 16.821us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
flash_ctrl_shadow_reg_errors 16.810s 16.821us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
flash_ctrl_shadow_reg_errors 16.810s 16.821us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
flash_ctrl_shadow_reg_errors_with_csr_rw 17.660s 592.017us 1 1 100.00
tl_intg_err 2 2 100.00
flash_ctrl_sec_cm 1784.360s 2943.200us 1 1 100.00
flash_ctrl_tl_intg_err 417.180s 1042.176us 1 1 100.00
sec_cm_reg_bus_integrity 1 1 100.00
flash_ctrl_tl_intg_err 417.180s 1042.176us 1 1 100.00
sec_cm_host_bus_integrity 1 1 100.00
flash_ctrl_tl_intg_err 417.180s 1042.176us 1 1 100.00
sec_cm_mem_bus_integrity 2 2 100.00
flash_ctrl_rd_intg 14.660s 76.144us 1 1 100.00
flash_ctrl_wr_intg 7.340s 185.356us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
flash_ctrl_smoke 80.940s 28.228us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 4 4 100.00
flash_ctrl_otp_reset 59.790s 41.844us 1 1 100.00
flash_ctrl_disable 14.670s 34.460us 1 1 100.00
flash_ctrl_sec_info_access 49.060s 2975.970us 1 1 100.00
flash_ctrl_connect 8.740s 25.136us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
flash_ctrl_config_regwen 6.520s 77.467us 1 1 100.00
sec_cm_data_regions_config_regwen 1 1 100.00
flash_ctrl_csr_rw 9.560s 34.337us 1 1 100.00
sec_cm_data_regions_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 16.810s 16.821us 1 1 100.00
sec_cm_info_regions_config_regwen 1 1 100.00
flash_ctrl_csr_rw 9.560s 34.337us 1 1 100.00
sec_cm_info_regions_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 16.810s 16.821us 1 1 100.00
sec_cm_bank_config_regwen 1 1 100.00
flash_ctrl_csr_rw 9.560s 34.337us 1 1 100.00
sec_cm_bank_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 16.810s 16.821us 1 1 100.00
sec_cm_mem_ctrl_global_esc 1 1 100.00
flash_ctrl_disable 14.670s 34.460us 1 1 100.00
sec_cm_mem_ctrl_local_esc 2 2 100.00
flash_ctrl_rd_intg 14.660s 76.144us 1 1 100.00
flash_ctrl_access_after_disable 6.400s 21.645us 1 1 100.00
sec_cm_mem_addr_infection 1 1 100.00
flash_ctrl_host_addr_infection 15.160s 93.176us 1 1 100.00
sec_cm_mem_disable_config_mubi 1 1 100.00
flash_ctrl_disable 14.670s 34.460us 1 1 100.00
sec_cm_exec_config_redun 1 1 100.00
flash_ctrl_fetch_code 10.850s 284.767us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
flash_ctrl_rw 384.550s 18230.189us 1 1 100.00
sec_cm_mem_integrity 3 3 100.00
flash_ctrl_rw_serr 163.650s 18754.179us 1 1 100.00
flash_ctrl_rw_derr 151.730s 4826.041us 1 1 100.00
flash_ctrl_integrity 319.090s 4707.640us 1 1 100.00
sec_cm_rma_entry_mem_sec_wipe 1 1 100.00
flash_ctrl_hw_rma 1201.510s 355945.228us 1 1 100.00
sec_cm_ctrl_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1784.360s 2943.200us 1 1 100.00
sec_cm_phy_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1784.360s 2943.200us 1 1 100.00
sec_cm_phy_prog_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1784.360s 2943.200us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
flash_ctrl_sec_cm 1784.360s 2943.200us 1 1 100.00
sec_cm_phy_arbiter_ctrl_redun 1 1 100.00
flash_ctrl_phy_arb_redun 9.660s 833.344us 1 1 100.00
sec_cm_phy_host_grant_ctrl_consistency 1 1 100.00
flash_ctrl_phy_host_grant_err 7.070s 79.109us 1 1 100.00
sec_cm_phy_ack_ctrl_consistency 1 1 100.00
flash_ctrl_phy_ack_consistency 9.320s 51.545us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
flash_ctrl_sec_cm 1784.360s 2943.200us 1 1 100.00
sec_cm_mem_tl_lc_gate_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1784.360s 2943.200us 1 1 100.00
sec_cm_prog_tl_lc_gate_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1784.360s 2943.200us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
asymmetric_read_path 1 1 100.00
flash_ctrl_rd_ooo 27.410s 1098.044us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
flash_ctrl_basic_rw 331.660s 5679.799us 1 1 100.00

Error Messages

   Test seed line log context
Job timed out after * minutes 1 test run
flash_ctrl_serr_counter 23327557241081552825197825982717777315258486291654939441528222138069594276799 None