Simulation Results: hmac

 
10/08/2026 15:30:36 DVSim: v1.50.1 sha: af43bb2 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 79.77 %
  • code
  • 97.85 %
  • assert
  • 97.38 %
  • func
  • 44.07 %
  • line
  • 99.69 %
  • branch
  • 99.17 %
  • cond
  • 96.29 %
  • toggle
  • 100.00 %
  • FSM
  • 94.12 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
hmac_smoke 3.730s 377.041us 1 1 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 0.900s 17.978us 1 1 100.00
csr_rw 1 1 100.00
hmac_csr_rw 0.850s 441.275us 1 1 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 12.870s 7678.640us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 4.790s 387.825us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 1.540s 75.586us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
hmac_csr_rw 0.850s 441.275us 1 1 100.00
hmac_csr_aliasing 4.790s 387.825us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 1 1 100.00
hmac_long_msg 23.470s 5806.453us 1 1 100.00
back_pressure 1 1 100.00
hmac_back_pressure 22.030s 1338.763us 1 1 100.00
test_vectors 6 6 100.00
hmac_test_sha256_vectors 8.740s 971.195us 1 1 100.00
hmac_test_sha384_vectors 353.630s 15491.083us 1 1 100.00
hmac_test_sha512_vectors 21.300s 1969.705us 1 1 100.00
hmac_test_hmac256_vectors 7.970s 331.250us 1 1 100.00
hmac_test_hmac384_vectors 10.030s 5737.951us 1 1 100.00
hmac_test_hmac512_vectors 8.060s 1121.972us 1 1 100.00
burst_wr 1 1 100.00
hmac_burst_wr 6.250s 764.901us 1 1 100.00
datapath_stress 1 1 100.00
hmac_datapath_stress 601.140s 63129.395us 1 1 100.00
error 1 1 100.00
hmac_error 24.460s 760.421us 1 1 100.00
wipe_secret 1 1 100.00
hmac_wipe_secret 75.140s 34213.918us 1 1 100.00
save_and_restore 6 6 100.00
hmac_smoke 3.730s 377.041us 1 1 100.00
hmac_long_msg 23.470s 5806.453us 1 1 100.00
hmac_back_pressure 22.030s 1338.763us 1 1 100.00
hmac_datapath_stress 601.140s 63129.395us 1 1 100.00
hmac_burst_wr 6.250s 764.901us 1 1 100.00
hmac_stress_all 69.200s 17495.077us 1 1 100.00
fifo_empty_status_interrupt 11 11 100.00
hmac_smoke 3.730s 377.041us 1 1 100.00
hmac_long_msg 23.470s 5806.453us 1 1 100.00
hmac_back_pressure 22.030s 1338.763us 1 1 100.00
hmac_datapath_stress 601.140s 63129.395us 1 1 100.00
hmac_wipe_secret 75.140s 34213.918us 1 1 100.00
hmac_test_sha256_vectors 8.740s 971.195us 1 1 100.00
hmac_test_sha384_vectors 353.630s 15491.083us 1 1 100.00
hmac_test_sha512_vectors 21.300s 1969.705us 1 1 100.00
hmac_test_hmac256_vectors 7.970s 331.250us 1 1 100.00
hmac_test_hmac384_vectors 10.030s 5737.951us 1 1 100.00
hmac_test_hmac512_vectors 8.060s 1121.972us 1 1 100.00
wide_digest_configurable_key_length 14 14 100.00
hmac_smoke 3.730s 377.041us 1 1 100.00
hmac_long_msg 23.470s 5806.453us 1 1 100.00
hmac_back_pressure 22.030s 1338.763us 1 1 100.00
hmac_datapath_stress 601.140s 63129.395us 1 1 100.00
hmac_burst_wr 6.250s 764.901us 1 1 100.00
hmac_error 24.460s 760.421us 1 1 100.00
hmac_wipe_secret 75.140s 34213.918us 1 1 100.00
hmac_test_sha256_vectors 8.740s 971.195us 1 1 100.00
hmac_test_sha384_vectors 353.630s 15491.083us 1 1 100.00
hmac_test_sha512_vectors 21.300s 1969.705us 1 1 100.00
hmac_test_hmac256_vectors 7.970s 331.250us 1 1 100.00
hmac_test_hmac384_vectors 10.030s 5737.951us 1 1 100.00
hmac_test_hmac512_vectors 8.060s 1121.972us 1 1 100.00
hmac_stress_all 69.200s 17495.077us 1 1 100.00
stress_all 1 1 100.00
hmac_stress_all 69.200s 17495.077us 1 1 100.00
alert_test 1 1 100.00
hmac_alert_test 0.670s 39.237us 1 1 100.00
intr_test 1 1 100.00
hmac_intr_test 0.710s 61.276us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
hmac_tl_errors 2.300s 244.868us 1 1 100.00
tl_d_illegal_access 1 1 100.00
hmac_tl_errors 2.300s 244.868us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
hmac_csr_hw_reset 0.900s 17.978us 1 1 100.00
hmac_csr_rw 0.850s 441.275us 1 1 100.00
hmac_csr_aliasing 4.790s 387.825us 1 1 100.00
hmac_same_csr_outstanding 2.260s 269.810us 1 1 100.00
tl_d_partial_access 4 4 100.00
hmac_csr_hw_reset 0.900s 17.978us 1 1 100.00
hmac_csr_rw 0.850s 441.275us 1 1 100.00
hmac_csr_aliasing 4.790s 387.825us 1 1 100.00
hmac_same_csr_outstanding 2.260s 269.810us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
hmac_sec_cm 1.080s 64.765us 1 1 100.00
hmac_tl_intg_err 2.080s 186.683us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
hmac_tl_intg_err 2.080s 186.683us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 1 1 100.00
hmac_smoke 3.730s 377.041us 1 1 100.00
stress_reset 1 1 100.00
hmac_stress_reset 0.980s 17.186us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
hmac_stress_all_with_rand_reset 82.650s 4551.664us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 2.940s 214.948us 1 1 100.00