Simulation Results

Simulation Results: i2c

10/08/2026 15:30:36 DVSim: v1.50.1 sha: af43bb2 json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
85.60 %

code
78.69 %

assert
97.46 %

func
80.66 %

line
96.69 %

branch
92.48 %

cond
85.19 %

toggle
73.87 %

FSM
45.24 %

Validation stages

V1		100.00%
V2		87.80%
V2S		100.00%
V3		0.00%

7/7 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_smoke				1	1	100.00
	i2c_host_smoke	19.790s	7188.133us	1	1	100.00
target_smoke				1	1	100.00
	i2c_target_smoke	18.830s	13281.200us	1	1	100.00
csr_hw_reset				1	1	100.00
	i2c_csr_hw_reset	0.810s	27.509us	1	1	100.00
csr_rw				1	1	100.00
	i2c_csr_rw	0.690s	20.789us	1	1	100.00
csr_bit_bash				1	1	100.00
	i2c_csr_bit_bash	3.430s	161.952us	1	1	100.00
csr_aliasing				1	1	100.00
	i2c_csr_aliasing	1.680s	141.576us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	i2c_csr_mem_rw_with_rand_reset	1.030s	135.361us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	i2c_csr_rw	0.690s	20.789us	1	1	100.00
	i2c_csr_aliasing	1.680s	141.576us	1	1	100.00

36/41 passed

87.80 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_error_intr				0	1	0.00
	i2c_host_error_intr	1.290s	442.824us	0	1	0.00
host_stress_all				1	1	100.00
	i2c_host_stress_all	435.340s	12750.751us	1	1	100.00
host_maxperf				1	1	100.00
	i2c_host_perf	338.040s	54146.832us	1	1	100.00
host_override				1	1	100.00
	i2c_host_override	0.740s	34.477us	1	1	100.00
host_fifo_watermark				1	1	100.00
	i2c_host_fifo_watermark	54.140s	4503.089us	1	1	100.00
host_fifo_overflow				1	1	100.00
	i2c_host_fifo_overflow	93.350s	2558.180us	1	1	100.00
host_fifo_reset				3	3	100.00
	i2c_host_fifo_reset_fmt	0.950s	143.626us	1	1	100.00
	i2c_host_fifo_fmt_empty	3.250s	1022.640us	1	1	100.00
	i2c_host_fifo_reset_rx	3.950s	771.856us	1	1	100.00
host_fifo_full				1	1	100.00
	i2c_host_fifo_full	34.310s	23164.631us	1	1	100.00
host_timeout				1	1	100.00
	i2c_host_stretch_timeout	5.420s	829.691us	1	1	100.00
i2c_host_mode_toggle				0	1	0.00
	i2c_host_mode_toggle	0.640s	7.335us	0	1	0.00
target_glitch				0	1	0.00
	i2c_target_glitch	2.010s	392.605us	0	1	0.00
target_stress_all				1	1	100.00
	i2c_target_stress_all	113.700s	35489.038us	1	1	100.00
target_maxperf				1	1	100.00
	i2c_target_perf	3.170s	2961.012us	1	1	100.00
target_fifo_empty				2	2	100.00
	i2c_target_stress_rd	11.820s	915.834us	1	1	100.00
	i2c_target_intr_smoke	4.220s	2163.620us	1	1	100.00
target_fifo_reset				2	2	100.00
	i2c_target_fifo_reset_acq	0.860s	282.106us	1	1	100.00
	i2c_target_fifo_reset_tx	2.050s	227.190us	1	1	100.00
target_fifo_full				3	3	100.00
	i2c_target_stress_wr	28.560s	33675.333us	1	1	100.00
	i2c_target_stress_rd	11.820s	915.834us	1	1	100.00
	i2c_target_intr_stress_wr	11.550s	13273.510us	1	1	100.00
target_timeout				1	1	100.00
	i2c_target_timeout	5.310s	1940.192us	1	1	100.00
target_clock_stretch				0	1	0.00
	i2c_target_stretch	3.600s	10054.406us	0	1	0.00
bad_address				1	1	100.00
	i2c_target_bad_addr	4.660s	1245.081us	1	1	100.00
target_mode_glitch				0	1	0.00
	i2c_target_hrst	4.660s	10134.304us	0	1	0.00
target_fifo_watermark				2	2	100.00
	i2c_target_fifo_watermarks_acq	2.170s	1619.325us	1	1	100.00
	i2c_target_fifo_watermarks_tx	1.110s	721.229us	1	1	100.00
host_mode_config_perf				2	2	100.00
	i2c_host_perf	338.040s	54146.832us	1	1	100.00
	i2c_host_perf_precise	8.430s	2641.325us	1	1	100.00
host_mode_clock_stretching				1	1	100.00
	i2c_host_stretch_timeout	5.420s	829.691us	1	1	100.00
target_mode_tx_stretch_ctrl				1	1	100.00
	i2c_target_tx_stretch_ctrl	2.520s	146.862us	1	1	100.00
target_mode_nack_generation				3	3	100.00
	i2c_target_nack_acqfull	1.810s	481.037us	1	1	100.00
	i2c_target_nack_acqfull_addr	1.710s	1729.498us	1	1	100.00
	i2c_target_nack_txstretch	1.520s	153.557us	1	1	100.00
host_mode_halt_on_nak				1	1	100.00
	i2c_host_may_nack	4.350s	525.877us	1	1	100.00
target_mode_smbus_maxlen				1	1	100.00
	i2c_target_smbus_maxlen	1.950s	562.563us	1	1	100.00
alert_test				1	1	100.00
	i2c_alert_test	0.900s	36.364us	1	1	100.00
intr_test				1	1	100.00
	i2c_intr_test	0.930s	20.025us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	i2c_tl_errors	2.390s	50.662us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	i2c_tl_errors	2.390s	50.662us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	i2c_csr_hw_reset	0.810s	27.509us	1	1	100.00
	i2c_csr_rw	0.690s	20.789us	1	1	100.00
	i2c_csr_aliasing	1.680s	141.576us	1	1	100.00
	i2c_same_csr_outstanding	1.170s	26.140us	1	1	100.00
tl_d_partial_access				4	4	100.00
	i2c_csr_hw_reset	0.810s	27.509us	1	1	100.00
	i2c_csr_rw	0.690s	20.789us	1	1	100.00
	i2c_csr_aliasing	1.680s	141.576us	1	1	100.00
	i2c_same_csr_outstanding	1.170s	26.140us	1	1	100.00

V2S

2/2 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	i2c_tl_intg_err	1.960s	559.981us	1	1	100.00
	i2c_sec_cm	1.000s	150.537us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	i2c_tl_intg_err	1.960s	559.981us	1	1	100.00

0/3 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Total
host_stress_all_with_rand_reset				1
	i2c_host_stress_all_with_rand_reset	16.710s	1023.945us	1
target_error_intr				1
	i2c_target_unexp_stop	1.290s	365.470us	1
target_stress_all_with_rand_reset				1
	i2c_target_stress_all_with_rand_reset	18.450s	6791.697us	1

Error Messages

	Test	seed	line	log context
UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between				3 test runs
	i2c_host_error_intr	75999687059613891186909272505396037193727188477955328041879151672043072264405	128	UVM_INFO @ 442824015 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	i2c_target_stress_all_with_rand_reset	97142702030878022658075949595296493470623512183674066283875977912922789701845	121	UVM_INFO @ 6791697350 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	i2c_host_mode_toggle	68584752065437882993028035440755209158636036018294665153586102753445721258149	81	UVM_INFO @ 7335426 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between				1 test run
	i2c_target_glitch	28560982981189469221463529914344809132071326736277889985712574384852693911766	84	UVM_INFO @ 392605017 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!				1 test run
	i2c_target_stretch	115444729597790673572744589836126025412368409916258367118933447529567687237751	78	UVM_INFO @ 10054406490 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (i2c_base_vseq.sv:1382) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [] vs [*])				1 test run
	i2c_target_unexp_stop	25661538643656151157662959528444771893561440977718181941559645121897816688595	78	UVM_INFO @ 365470106 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!				1 test run
	i2c_target_hrst	97228771215792503217956354504861746174513765102100239010887220949471412150457	79	UVM_INFO @ 10134304437 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1286) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.				1 test run
	i2c_host_stress_all_with_rand_reset	69691465290709112813076617296286099054992695240649642187864851745347607534413	92	UVM_INFO @ 1023945107 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---