Simulation Results: lc_ctrl/volatile_unlock_disabled

 
10/08/2026 15:30:36 DVSim: v1.50.1 sha: af43bb2 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 90.78 %
  • code
  • 84.11 %
  • assert
  • 94.69 %
  • func
  • 93.55 %
  • line
  • 97.24 %
  • branch
  • 93.70 %
  • cond
  • 79.29 %
  • toggle
  • 87.68 %
  • FSM
  • 62.62 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 1.430s 54.216us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 1.250s 42.172us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 0.970s 102.421us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.210s 47.471us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.370s 114.938us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.670s 33.821us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 0.970s 102.421us 1 1 100.00
lc_ctrl_csr_aliasing 1.370s 114.938us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 4.680s 704.830us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 4.740s 1194.341us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 0.940s 45.821us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 1.910s 125.107us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 8.270s 1307.627us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 4.330s 234.992us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 8.270s 1307.627us 1 1 100.00
lc_ctrl_prog_failure 1.910s 125.107us 1 1 100.00
lc_ctrl_errors 4.330s 234.992us 1 1 100.00
lc_ctrl_security_escalation 4.590s 1151.807us 1 1 100.00
lc_ctrl_jtag_state_failure 23.990s 1989.433us 1 1 100.00
lc_ctrl_jtag_prog_failure 3.790s 610.324us 1 1 100.00
lc_ctrl_jtag_errors 32.690s 8865.516us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 2.120s 512.096us 1 1 100.00
lc_ctrl_jtag_state_post_trans 7.750s 324.394us 1 1 100.00
lc_ctrl_jtag_prog_failure 3.790s 610.324us 1 1 100.00
lc_ctrl_jtag_errors 32.690s 8865.516us 1 1 100.00
lc_ctrl_jtag_access 2.010s 531.274us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 7.900s 1676.223us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 1.900s 78.086us 1 1 100.00
lc_ctrl_jtag_csr_rw 1.130s 790.213us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 4.110s 477.360us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 3.700s 2115.870us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 0.880s 27.721us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 1.270s 261.132us 1 1 100.00
lc_ctrl_jtag_alert_test 1.440s 603.655us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 3.190s 330.897us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 0.880s 22.266us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 32.530s 7250.977us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 1.050s 24.784us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 1.280s 89.155us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 1.280s 89.155us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.250s 42.172us 1 1 100.00
lc_ctrl_csr_rw 0.970s 102.421us 1 1 100.00
lc_ctrl_csr_aliasing 1.370s 114.938us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.260s 47.614us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.250s 42.172us 1 1 100.00
lc_ctrl_csr_rw 0.970s 102.421us 1 1 100.00
lc_ctrl_csr_aliasing 1.370s 114.938us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.260s 47.614us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 6.570s 2548.720us 1 1 100.00
lc_ctrl_tl_intg_err 1.220s 126.453us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 1.220s 126.453us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 4.740s 1194.341us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 8.270s 1307.627us 1 1 100.00
lc_ctrl_sec_cm 6.570s 2548.720us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 8.270s 1307.627us 1 1 100.00
lc_ctrl_sec_cm 6.570s 2548.720us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 8.270s 1307.627us 1 1 100.00
lc_ctrl_sec_cm 6.570s 2548.720us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 8.270s 1307.627us 1 1 100.00
lc_ctrl_sec_cm 6.570s 2548.720us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 8.270s 1307.627us 1 1 100.00
lc_ctrl_sec_cm 6.570s 2548.720us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 8.270s 1307.627us 1 1 100.00
lc_ctrl_sec_cm 6.570s 2548.720us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 8.270s 1307.627us 1 1 100.00
lc_ctrl_sec_cm 6.570s 2548.720us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 8.270s 1307.627us 1 1 100.00
lc_ctrl_sec_cm 6.570s 2548.720us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 4.590s 1151.807us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 4.680s 704.830us 1 1 100.00
lc_ctrl_jtag_state_post_trans 7.750s 324.394us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 6.530s 1055.851us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 6.530s 1055.851us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 5.340s 1307.371us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 4.220s 737.334us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 4.220s 737.334us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
lc_ctrl_stress_all_with_rand_reset 15.000s 1156.163us 1 1 100.00